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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8025ffc700bsm44091127b3.36.2026.06.23.06.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2026 06:05:29 -0700 (PDT) From: Qiang Yu Date: Tue, 23 Jun 2026 06:05:18 -0700 Subject: [PATCH v2 2/3] phy: qcom: qmp-pcie: Add vdda-refgen supplies for Glymur Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260623-phy_refgen-v2-2-4d15983bf91d@oss.qualcomm.com> References: <20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com> In-Reply-To: <20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782219925; l=1908; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=sb3Uq6ABumgwjZWgmUAldF69UC0Cn8aYOQo27nojvoQ=; b=lccl7A4IcciL4lCF44EqI5hyhq94HvqgY9ftKfLfzIZ0mHnucEkAgZ+GqhMJK9q3M8A/GlLk/ z+ZdNTNpUopB/fYRJbsUZXijtJpSXV9Qk6RUmak86gaNsU7K5SFHPDv X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIzMDEwNyBTYWx0ZWRfX1rMIVXELFXz6 raNhCHZEef+tURjs77FwEFpcywRcQWgpMrQf9iF4pnnxE2B4ohPoZNtj8Km5ZNHKwRE/6llfzDO Drh4epopwcu5X2kscWYNEpNf8UwKXPqMuK1/Kc/2t/qcGMitgyI2V6lH7uGuZBsMl9xc/G/bCUI fCtLoVH6K6w0gwoI1H2z4RKdzcXSpeQ3iOzpL29WgdQaCAJYdhVd9TT0VyEXurGtLFozF/XEq/G fiQCQrfeM0PaSBTfBjbFlDC9gCwSXo80mwl9r7z64lGvZiCKfiUww7d5qR1o11isJs4BxJhDsN3 JgApQxipbP3+FEO6ZUzrhh7CQltmgirJ6WrX22hsVGEyPAZSbxx9K/BctvAucZuV9aUgqukaHLb Rrp59y6PV2g4bZxSLaPYuzRpyj6KheDnM8t9GPG2YLScSg7abs15FybzQ++6p3UzKsmHVLOtWRp 2Et4abSpSil96bLaH7w== X-Proofpoint-GUID: V_7Se0IqI3WgwggqFap-rbmoP2U--HCc X-Authority-Analysis: v=2.4 cv=dvfrzVg4 c=1 sm=1 tr=0 ts=6a3a849b cx=c_pps a=NMvoxGxYzVyQPkMeJjVPKg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=m2jQVEIWa0EwQwJFt7gA:9 a=QEXdDO2ut3YA:10 a=kLokIza1BN8a-hAJ3hfR:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIzMDEwNyBTYWx0ZWRfX5BTv15wgFlN+ ZlcVpdAN0ROI9MNqh/ftzfjJu/xRL63g1J7kypydaOKks79Nc3JraYIrR9sBn6bpie0KyElLuKe Y3mDoJCzFfgaBb+fWCuELTfLEYIV5eg= X-Proofpoint-ORIG-GUID: V_7Se0IqI3WgwggqFap-rbmoP2U--HCc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-23_03,2026-06-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606230107 The refgen providing reference voltage for PCIe QMP PHY on Glymur requires two power supplies independent from the PHY's core and qref rails. Add support for vdda-refgen0p9 and vdda-refgen1p2 supplies with a dedicated glymur_qmp_phy_vreg_l list. Update both Gen5x4 and Gen4x2 configurations to use the new supply list. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index d3effad7a074..08bc89ce80e1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3488,6 +3488,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", "vdda-qref", }; +static const char * const glymur_qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", +}; + /* list of resets */ static const char * const ipq8074_pciephy_reset_l[] = { "phy", "common", @@ -4756,8 +4760,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = glymur_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(glymur_qmp_phy_vreg_l), .regs = pciephy_v8_50_regs_layout, @@ -4772,8 +4776,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = glymur_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(glymur_qmp_phy_vreg_l), .regs = pciephy_v8_regs_layout, -- 2.34.1