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Tue, 23 Jun 2026 07:08:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB89.mail.protection.outlook.com (10.167.253.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.159.10 via Frontend Transport; Tue, 23 Jun 2026 07:08:08 +0000 Received: from cix (unknown [172.18.64.61]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 55F8440E7F93; Tue, 23 Jun 2026 15:08:07 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, gary.yang@cixtech.com Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang Subject: [PATCH v6 0/4] Add Cix Sky1 AUDSS clock and reset support Date: Tue, 23 Jun 2026 15:08:01 +0800 Message-ID: <20260623070805.211019-1-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB89:EE_|SEZPR06MB5521:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: b37b307b-817e-465e-24a1-08ded0f62e76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|376014|7416014|1800799024|18002099003|56012099006|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: D2/4XbvdE4fEGmxePe/JDxLOeJaz7DcontwV3rm5HxLx4tBjIm8ZmHBICFSQ/RbKXbSQJ9hgPq3YRSGcs5MdRqFfF77b5M4g4yNerUc8IYxr8TiyIh5kUNaCe6HRZeRXmWZY8H9c0Y/61CuVO8Y4hCP2DRTvr8U061BXrekyS7DEtysOhs9mDcHDsHHC7vlnTh9bpfFqBOVG9r+G7zzyms/buTW/Zc3Db4PonjtCIFWt3bvGXFGgb8ZNGny/tFPUZukPV1dTKEqnEi5m6tGg1u6EU4POJhsH8FV4Lg19nII83FovcYicLvvYwH+9GnQgKH4fCknELf3AejC7u6Bd/5uNWyzgvAQZymf/K4DnREsVDuwQg9ItbSi/6lUyn4PUC+cUwWHcoOsJ2yJ49/8PEuYCsDQeMuCVZ5Jy2i0UX/cmFoyND7W1s7TaPUZr6eUQ X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2026 07:08:08.9059 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b37b307b-817e-465e-24a1-08ded0f62e76 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB89.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB5521 From: Joakim Zhang The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related blocks such as HDA, I2S, DSP, DMA, mailboxes, watchdog and timer behind one Clock and Reset Unit (CRU). The CRU is a single MMIO register block that provides clock muxing, gating and block-level software reset lines for those peripherals. Clock and reset support are submitted in one series because they belong to the same hardware block and share one devicetree node (cix,sky1-audss-cru). The binding, clock indices and reset indices are defined together; the clock driver maps the CRU and instantiates the reset controller as an auxiliary driver on that node. Splitting clk and reset across separate series would leave neither side self-contained: the DTS node needs both providers, and the reset driver has no standalone probe path without the clock driver. --- ChangeLogs: v5->v6: * rename dt-bindings headers to cix,sky1-audss-cru.h to match compatible * drop status = "okay" from audss_cru node in sky1.dtsi v4->v5: * refactor the driver, using platform_driver for clk and auxiliary_driver for reset. v3->v4: * move both power domain and resets into parset node (audss_cru) * remove "simple-mfd", and change to populate the child node * cix,sky1-audss.h -> cix,sky1-audss-clock.h v2->v3: * clk part: * devm_reset_control_get()->devm_reset_control_get_exclusive() * assert noc reset from suspend * clock parents changes from 6 to 4, and rename the clock names, explain more about this: confirm with our designer, In fact, there are 6 clock sources going into the audio subsystem. audio_clk1 and audio_clk3 are redundant in design and are not actually needed in practice, so they are not shown here. * refine clocks and clock-names property * add detailed description of clocks * drop parent node from clk binding * drop define AUDSS_MAX_CLKS * reset part: * rename reset signal macro, remove _N * drop SKY1_AUDSS_SW_RESET_NUM * switching to compatible-style of defining subnodes in parent schema v1->v2: * remove audss_rst device node since it doesn't has resource, and move to reset-sky1.c driver. * remove hda related which would be sent after this patch set accepted * soc componnet is okay by default from dtsi * fix for audss clk driver: * remove "comment "Clock options for Cixtech audss:"" * add select MFD_SYSCON * move lock and clk_data into struct sky1_audss_clks_priv * const char *name -> const char * const * name * remove CLK_GET_RATE_NOCACHE * divicer -> divider * Reverse Christmas tree order * return reg ? 1 : 0; -> return !!reg; * return ERR_CAST(hw); -> return hw; * of_device_get_match_data(dev) -> device_get_match_data() * add lock from runtime_suspend/resume * loop to more mailing lists Joakim Zhang (4): dt-bindings: soc: cix: add sky1 audss cru controller clk: cix: add sky1 audss clock controller reset: cix: add sky1 audss auxiliary reset driver arm64: dts: cix: sky1: add audss cru .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 92 ++ arch/arm64/boot/dts/cix/sky1.dtsi | 18 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/cix/Kconfig | 16 + drivers/clk/cix/Makefile | 3 + drivers/clk/cix/clk-sky1-audss.c | 1201 +++++++++++++++++ drivers/reset/Kconfig | 14 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1-audss.c | 192 +++ .../dt-bindings/clock/cix,sky1-audss-cru.h | 60 + .../dt-bindings/reset/cix,sky1-audss-cru.h | 25 + 12 files changed, 1624 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml create mode 100644 drivers/clk/cix/Kconfig create mode 100644 drivers/clk/cix/Makefile create mode 100644 drivers/clk/cix/clk-sky1-audss.c create mode 100644 drivers/reset/reset-sky1-audss.c create mode 100644 include/dt-bindings/clock/cix,sky1-audss-cru.h create mode 100644 include/dt-bindings/reset/cix,sky1-audss-cru.h -- 2.50.1