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Thu, 25 Jun 2026 01:25:18 -0700 (PDT) Received: from xeon ([188.163.112.61]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3999af9f3a9sm39064081fa.7.2026.06.25.01.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 01:25:18 -0700 (PDT) From: Svyatoslav Ryhel To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Svyatoslav Ryhel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/1] gpu/drm: bridge: tc358768: Add delay after PLL setup Date: Thu, 25 Jun 2026 11:25:06 +0300 Message-ID: <20260625082507.57703-1-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes up, the DSI register sequence runs near immediately. On TF700T this results in the bridge claiming PLL lock but producing no DSI video output: the panel powers up, the backlight comes on, but the framebuffer is never scanned out. Insert a small settling delay between PLL setup and the rest of the attach. --- - switched sleep() > delay() since *_pre_enable() is atomic --- Svyatoslav Ryhel (1): gpu/drm: bridge: tc358768: Add delay after PLL setup drivers/gpu/drm/bridge/tc358768.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.53.0