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Thu, 25 Jun 2026 01:25:19 -0700 (PDT) From: Svyatoslav Ryhel To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Svyatoslav Ryhel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/1] gpu/drm: bridge: tc358768: Add delay after PLL setup Date: Thu, 25 Jun 2026 11:25:07 +0300 Message-ID: <20260625082507.57703-2-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260625082507.57703-1-clamor95@gmail.com> References: <20260625082507.57703-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes up, the DSI register sequence runs near immediately. On TF700T this results in the bridge claiming PLL lock but producing no DSI video output: the panel powers up, the backlight comes on, but the framebuffer is never scanned out. Insert a small settling delay between PLL setup and the rest of the attach. Suggested-by: Michele Brocco Tested-by: Michele Brocco # TF700T Signed-off-by: Svyatoslav Ryhel --- drivers/gpu/drm/bridge/tc358768.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 0f2820b37302..ea358c8da0e9 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -824,6 +824,9 @@ static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge, return; } + /* Allow the PLL to settle */ + mdelay(20); + drm_display_mode_to_videomode(mode, &vm); dsiclk = priv->dsiclk; -- 2.53.0