From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBBD9225413 for ; Thu, 25 Jun 2026 09:45:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.50 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782380706; cv=none; b=CuO7lqgA9p08GVKhTddtRVxFvACEo/IF8Je7mExHlZ+nGobKbOfy/ZrX/GjUEFwLAOmyeMYnbESG8RbFE7h6OpOqnU3qWjyh5+x4B4winFXhZMyaUma2iZWqK5JXVvnCxDPuLPicgxDfL/4JuG4X0v+qX3Mwz/rw0AdexF9XG4c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782380706; c=relaxed/simple; bh=xzXCpNn8k2uKryu96PqnMaA1WoxyVAdEv3c6jZ2QYYg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uVfAPJuiy+cb8m8ZoC4UBiyT2rNae7QMOla3puk+BbF4dIvUYjZttSwvWkmM4iI83X94TYV+uJOvpwXm/o6JNrIsV45/8VrXrgccxF5EupSevMU53riwICXAFyGO7vyJzeTlK+dZ94VhhRSKwNIEMd0xTnJwA5lhKMUEF5lBzZ4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kft31trA; arc=none smtp.client-ip=209.85.216.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kft31trA" Received: by mail-pj1-f50.google.com with SMTP id 98e67ed59e1d1-37deb2d3a28so1184197a91.2 for ; Thu, 25 Jun 2026 02:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782380704; x=1782985504; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zG+ncOED8kJvI4v12/W3LY0+BgurY5fCH2pouNtIlDQ=; b=kft31trA/7AdswB/AurdwejphmPRWVBLm7CypEAAspSCdI/sBvhq2x+0254gN5qzpC U9jgLJFY/iC/xBmhrQR+SQpnC3ZGRgwngiYkyOubfmsQkq54SYX8T6HIBs4zFGV8S0GB T/PhmN77GQ4KtvbGp4wznRSQvITSLU0elMMtoc6Do3omSv+ju3VWLATFMtyX/wfsU9AG JE5GhIqHRU2Yi2bDAWgn/PLeOaKg5NBnnQPgVCFgZXJVbxsMLPMV7ZcDUWcfk0cYge/t XwexasHA903wIRXeHEQYHb7W9qlbEFC+8Hpk7zgfAYfqBZVUhQWMWepF0YV4jZD3v7sM HZSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782380704; x=1782985504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zG+ncOED8kJvI4v12/W3LY0+BgurY5fCH2pouNtIlDQ=; b=QOLlfhK5k5OgRCoCJbvTtvG5RzvyugfPEMSi7vzEgV+KhAkDWYSDrovUHbbc0qtrQm JoBu08uTgidsRWQubbQbm7Qy0UOEVLuCZtWyOs89kZua2sMqhGdoV9EhG9ssp/ph6s+u w85B0tZYQgHCzZoo1YiG5GwEfXf6kMVXuwC4vhMFfH/ns2Lazi//U/sRqYD+0SGodFys jwuvDpQYQS0NzSsU/0lJMfmoY1bfkcewrdYSRybsDxlZRFYjShiIN6gGtInOoj33BMVp 5r+wU27K5OVekCZ8fYTwmxO2xQ5XvF9gzamyzHj8tdbumOuoJ910Yu8lvxS59ut+hNHd tLJw== X-Forwarded-Encrypted: i=1; AHgh+RpWuEEtfJkHJ248afXryc8IYWmOO0mopBFphtM4vwm0ilDJayPYSSTkJnata15y7z2Ik3rImVpyEwwVevA=@vger.kernel.org X-Gm-Message-State: AOJu0Yz8d4re2hgSq15IjTRkjS6baCbr6EpMzyJWvuughP7UCwM2SWBK EN0xXpB+0HcXPB4bIxZeIRPzYmMmg9tnS+KNUUaQKFrkfx7rZzO4I/kF X-Gm-Gg: AfdE7cmKe2d+8phRpQWta2oPIPbzP2VaQfhyc5MM7j01I0abGgQU9gmdpFos5QifbLU spukRZdOrtngdhy9GzBE4PrYryXH34sESJM8k8Wt4rx6kXdW3Sst/YhV9by1aI0IYz0KBr93Ccn URcfCF0oQKckMMz/jzp9avE5dV5grqrR5GANO+43hjjB9+HuhL3BfbQEfTr2VAfnAlK1YYvVj9M hsGGre5A0rh83RXeebVG0OvYjREHJq6qjqAOTfoq2bAK4ZKCFNOKS9sO3jsb3BcsJ0nvSrx5IzW Ot6KT09O+DdogOMyW2dhlgGZeCH1GKOibg07kjPbCJfDNIXEwWN8qWJzs3QURVQsVLrzQTLEWyC ha99zJwDGg92XmGHQtdGORm+psNnV3sgMGzKFWTegqJcv/0In5cQIADuVDE7/wBZfr9NAvxg8Ga fiqPtdFRjJ5i2/+TGQIpS1URcQGrEOYhqHOsw1E388nmUMevc/NH4a+tRNiEX/aqLgcleEdrRbr w== X-Received: by 2002:a17:902:fc4b:b0:2c7:e318:1d86 with SMTP id d9443c01a7336-2c7fc6545f7mr18443535ad.1.1782380704007; Thu, 25 Jun 2026 02:45:04 -0700 (PDT) Received: from localhost.localdomain (60-250-196-139.hinet-ip.hinet.net. [60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f5ac8c26sm16614995ad.1.2026.06.25.02.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 02:45:03 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v5 2/7] drm/verisilicon: add register-level macros for DC8000 Date: Thu, 25 Jun 2026 17:44:44 +0800 Message-ID: <20260625094449.708386-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260625094449.708386-1-a0987203069@gmail.com> References: <20260625094449.708386-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add register-level constants needed by the forthcoming DC8000 (DCUltraLite) hardware ops: VSDC_DISP_IRQ_VSYNC(n) in vs_crtc_regs.h: bit mask for per-output VSYNC interrupt bits in DISP_IRQ_STA (0x147C) / DISP_IRQ_EN (0x1480), which are the IRQ registers used by DCUltraLite in place of the DC8200 TOP_IRQ_ACK / TOP_IRQ_EN registers. VSDC_FB_CONFIG_ENABLE (bit 0), VSDC_FB_CONFIG_VALID (bit 3) and VSDC_FB_CONFIG_RESET (bit 4) in vs_primary_plane_regs.h: control bits in the FB_CONFIG register used by DCUltraLite for framebuffer enable and per-frame commit handshake. No behaviour change for existing DC8200 platforms. Signed-off-by: Joey Lu Reviewed-by: Icenowy Zheng --- drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 1 + drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h index c7930e817635..d4da22b08cd5 100644 --- a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h +++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h @@ -54,6 +54,7 @@ #define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) #define VSDC_DISP_IRQ_STA 0x147C +#define VSDC_DISP_IRQ_VSYNC(n) BIT(n) #define VSDC_DISP_IRQ_EN 0x1480 diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h index cbb125c46b39..67d4b00f294e 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h @@ -16,6 +16,9 @@ #define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) #define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) +#define VSDC_FB_CONFIG_ENABLE BIT(0) +#define VSDC_FB_CONFIG_VALID BIT(3) +#define VSDC_FB_CONFIG_RESET BIT(4) #define VSDC_FB_CONFIG_CLEAR_EN BIT(8) #define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) #define VSDC_FB_CONFIG_ROT(v) ((v) << 11) -- 2.43.0