From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCE5B3E51CC for ; Thu, 25 Jun 2026 12:59:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782392396; cv=none; b=IiPj9XYsTZqBW4zEewSFe1+SdM75Rlp3Qb9sIg3v/Pu00ISjXOZjHcDdR5yt4va88BIKsOnzaqFW2U7juYLRwD3SfOXUOZBJx6zVdeInRdI5G2d7cSWsH+2eGndPTzbycz6TNTpH/L+pBNEmBwRoLJ/cJRovOtM3FheJESVcbgw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782392396; c=relaxed/simple; bh=Ju3gfzFeBeams+3Iev1BlEjXoqqkURWq1dmcBXf0Gac=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bKF/sKiTUBLHv9g6vpMJzxcpcNACPsyjB0FDYeq69XTy3jirlw5uzIBzZ+CqQRn0BJ23brLNnGGL1yQffgiKu90LvUkesimXsC0TcVMXRqLoFODSobukbpegQ3+xNEMXIYeRsGW7NvobyA1jfwd+K3SE1TSsNbJswNp+O68bZYM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A5BEGhfV; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A5BEGhfV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782392395; x=1813928395; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ju3gfzFeBeams+3Iev1BlEjXoqqkURWq1dmcBXf0Gac=; b=A5BEGhfVfytpQIq6leAUvNsq9YfW/tWHPXQHj7WV+tbMtctEgvNu/w/M PqXCm1wi33p4hCS3SILZiCplNoPvgcVP/pSMogNOdVzkkPNcnQAJnf4cs E4D+rsdUVBS0k3Iby3jUpd24MTyvSHMj5N6+kragNG9G/5HCKNkrQOSkt dZD5hgTNm/5fhxFwtWrzi6rfWTXLZnJTFZdiaj18iX6p6gZFLroUsHrvS oRl+oD1pk/B2ayl7+ViaxKfP0/K09gJssErz3BKo6wrUDQrzazhAMIz19 nM3Pg9lgBVgDQgcxSLIOoeUCyHRGVvzf2+wwbxKpD98oG1xoSZ5+q7NE6 Q==; X-CSE-ConnectionGUID: Ix3xt35rSga45aGn7nVc2w== X-CSE-MsgGUID: ovfYX5a7SWiC9vBlyvezYA== X-IronPort-AV: E=McAfee;i="6800,10657,11827"; a="82287396" X-IronPort-AV: E=Sophos;i="6.24,224,1774335600"; d="scan'208";a="82287396" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2026 05:59:54 -0700 X-CSE-ConnectionGUID: iyYEnqxrRCqiMDSh7gcxFQ== X-CSE-MsgGUID: JDi4aJs1SZSPji3+mUzr0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,224,1774335600"; d="scan'208";a="280857128" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa002.jf.intel.com with ESMTP; 25 Jun 2026 05:59:50 -0700 From: Heikki Krogerus To: Rodrigo Vivi Cc: Matthew Brost , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Raag Jadav , "Michael J . Ruhl" , Andy Shevchenko , Mika Westerberg , Riana Tauro , David Airlie , Simona Vetter , Andi Shyti , dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] drm/xe/mcu_i2c: Take over control of the controller enabling Date: Thu, 25 Jun 2026 14:59:39 +0200 Message-ID: <20260625125939.429078-4-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260625125939.429078-1-heikki.krogerus@linux.intel.com> References: <20260625125939.429078-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some platforms make an assumption that the i2c controller's enabled state indicates also the power state of the controller. This can create a problem when the controller is in disabled state, because the hardware may assume incorrectly that it is then also in low-power state. To fix this, the controller is kept enabled by taking over the IC_ENABLE register. The controller has to be disabled when the configuration is updated and when the target address or the slave address are assigned, so disabling it when IC_CON, IC_TAR or IC_SAR registers are programmed, and then re-enabling it again. Signed-off-by: Heikki Krogerus --- drivers/gpu/drm/xe/xe_i2c.c | 55 +++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/xe/xe_i2c.h | 1 + 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c index 0495b561957a2..e2d8e77653cf2 100644 --- a/drivers/gpu/drm/xe/xe_i2c.c +++ b/drivers/gpu/drm/xe/xe_i2c.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -294,11 +295,40 @@ static void xe_i2c_remove_irq(struct xe_i2c *i2c) irq_domain_remove(i2c->irqdomain); } +/* See "Disabling DW_apb_i2c" in the DesignWare DW_abp_i2c databook. */ +static void xe_i2c_disable(struct xe_i2c *i2c) +{ + int timeout = 100; + u32 status; + + xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), 1, 0); + + do { + status = xe_mmio_read32(i2c->mmio, I2C_REG(DW_IC_ENABLE_STATUS)); + if (!(status & 1)) + return; + /* Can't sleep here. */ + udelay(25); + } while (timeout--); + + dev_warn(&i2c->adapter->dev, "timeout in disabling adapter\n"); +} + static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) { struct xe_i2c *i2c = context; - *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); + *val = xe_mmio_read32(i2c->mmio, I2C_REG(reg)); + + switch (reg) { + case DW_IC_ENABLE: + case DW_IC_ENABLE_STATUS: + FIELD_MODIFY(DW_IC_ENABLE_ENABLE, val, + i2c->ic_enable & DW_IC_ENABLE_ENABLE); + break; + default: + break; + } return 0; } @@ -307,7 +337,28 @@ static int xe_i2c_write(void *context, unsigned int reg, unsigned int val) { struct xe_i2c *i2c = context; - xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); + switch (reg) { + case DW_IC_CON: + case DW_IC_TAR: + case DW_IC_SAR: + /* Disable the controller. */ + xe_i2c_disable(i2c); + + /* Write the register. */ + xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); + + /* Enable the controller. */ + xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), 0, 1); + break; + case DW_IC_ENABLE: + i2c->ic_enable = val; + /* Other fields can be updated except the enable bit. */ + val |= DW_IC_ENABLE_ENABLE; + fallthrough; + default: + xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); + break; + } return 0; } diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h index b3327db998708..231e36df09017 100644 --- a/drivers/gpu/drm/xe/xe_i2c.h +++ b/drivers/gpu/drm/xe/xe_i2c.h @@ -39,6 +39,7 @@ struct xe_i2c { struct platform_device *pdev; struct i2c_adapter *adapter; struct i2c_client *client[XE_I2C_MAX_CLIENTS]; + unsigned int ic_enable; struct notifier_block bus_notifier; struct work_struct work; -- 2.50.1