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(unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgCnDy2mGj5qJK5xDg--.41368S2; Fri, 26 Jun 2026 14:22:31 +0800 (CST) From: Xiaofeng Yuan To: pjw@kernel.org Cc: palmer@dabbelt.com, aou@eecs.berkeley.edu, namcao@linutronix.de, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xiaofeng Yuan Subject: [PATCH v3] riscv: probes: simulate c.jal instruction Date: Fri, 26 Jun 2026 06:22:28 +0000 Message-ID: <20260626062228.54873-1-xiaofengmian@163.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:PCgvCgCnDy2mGj5qJK5xDg--.41368S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxAFW5tFWDXryDXF4UXw1rCrg_yoW5Ary5pF s0k3Zxtrs8uFWkCr9xJrs3ur48Kws5K3ya9a18ta1Fgr1agryfZwn2ganxAFsrtrySgr97 G39IqrykA343JrDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pR3EfUUUUUU= X-CM-SenderInfo: p0ld0w5hqjzxldq6il2tof0z/xtbC5QfZ3Go+GqepDwAA3o The c.jal instruction is currently marked REJECTED in kprobes instruction decoding, but it should be SIMULATED like other compressed jump instructions. Add simulate_c_jal() which saves the return address to x1 (ra) and sets the program counter to the target offset, reusing simulate_c_j for the common jump logic. Signed-off-by: Xiaofeng Yuan --- v2: reuse simulate_c_j() for common jump logic (per Nam Cao's review) (resend: v2 had wrong diff) arch/riscv/kernel/probes/decode-insn.c | 2 +- arch/riscv/kernel/probes/simulate-insn.c | 8 ++++++++ arch/riscv/kernel/probes/simulate-insn.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/probes/decode-insn.c b/arch/riscv/kernel/probes/decode-insn.c index 65d9590bf..8506470e9 100644 --- a/arch/riscv/kernel/probes/decode-insn.c +++ b/arch/riscv/kernel/probes/decode-insn.c @@ -29,7 +29,7 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api) * TODO: the REJECTED ones below need to be implemented */ #ifdef CONFIG_RISCV_ISA_C - RISCV_INSN_REJECTED(c_jal, insn); + RISCV_INSN_SET_SIMULATE(c_jal, insn); RISCV_INSN_REJECTED(c_ebreak, insn); RISCV_INSN_SET_SIMULATE(c_j, insn); diff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c index fa581590c..6d7a5f949 100644 --- a/arch/riscv/kernel/probes/simulate-insn.c +++ b/arch/riscv/kernel/probes/simulate-insn.c @@ -163,6 +163,14 @@ bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs return true; } +bool __kprobes simulate_c_jal(u32 opcode, unsigned long addr, struct pt_regs *regs) +{ + if (!rv_insn_reg_set_val(regs, 1, addr + 2)) + return false; + + return simulate_c_j(opcode, addr, regs); +} + static bool __kprobes simulate_c_jr_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs, bool is_jalr) { diff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h index 44ebbc444..b89e1bb01 100644 --- a/arch/riscv/kernel/probes/simulate-insn.h +++ b/arch/riscv/kernel/probes/simulate-insn.h @@ -25,6 +25,7 @@ bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs); bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs); bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs); bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs); +bool simulate_c_jal(u32 opcode, unsigned long addr, struct pt_regs *regs); bool simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs); bool simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs); bool simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs); -- 2.43.0