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Sat, 27 Jun 2026 03:02:08 -0700 (PDT) Received: from hu-naala-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-139d90e95c6sm38446568c88.11.2026.06.27.03.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jun 2026 03:02:07 -0700 (PDT) From: Nabige Aala Date: Sat, 27 Jun 2026 15:31:36 +0530 Subject: [PATCH 2/5] arm64: dts: qcom: shikra-cqm-evk: Enable display and add ili7807s panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260627-shikra-dt-changes-v1-2-449a402673d0@oss.qualcomm.com> References: <20260627-shikra-dt-changes-v1-0-449a402673d0@oss.qualcomm.com> In-Reply-To: <20260627-shikra-dt-changes-v1-0-449a402673d0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arpit.saini@oss.qualcomm.com, mohit.dsor@oss.qualcomm.com, Nabige Aala X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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Pin pm4125_l5 to 1.232V with regulator-allow-set-load for DSI PHY PLL stability. Signed-off-by: Arpit Saini --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 104 ++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 683b5245923b..c9ea093cd8ca 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -23,6 +23,18 @@ chosen { stdout-path = "serial0:115200n8"; }; + lcd_bias: regulator-lcd-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_bias"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pm4125_l17>; + gpio = <&tlmm 151 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_bias_en>; + pinctrl-names = "default"; + }; + wcn3988-pmu { compatible = "qcom,wcn3988-pmu"; @@ -60,6 +72,52 @@ vreg_pmu_ch1: ldo4 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm4125_l5>; + status = "okay"; + + panel@0 { + compatible = "dlc,dlc0697", "ilitek,ili7807s"; + reg = <0>; + + reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + vddi-supply = <&pm4125_l15>; + avdd-supply = <&lcd_bias>; + avee-supply = <&lcd_bias>; + + pinctrl-0 = <&panel_bl_en &panel_rst_n &panel_te_pin>; + pinctrl-1 = <&panel_bl_en_suspend &panel_rst_n_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pm4125_l5 { + /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + regulator-allow-set-load; +}; + &remoteproc_cdsp { firmware-name = "qcom/shikra/cdsp.mbn"; @@ -116,3 +174,49 @@ &wifi { status = "okay"; }; + +&tlmm { + lcd_bias_en: lcd-bias-en-state { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + panel_bl_en: panel-bl-en-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + panel_bl_en_suspend: panel-bl-en-suspend-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + + panel_rst_n: panel-rst-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_rst_n_suspend: panel-rst-n-suspend-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_te_pin: panel-te-pin-state { + pins = "gpio86"; + function = "mdp_vsync_p"; + drive-strength = <2>; + bias-pull-down; + }; +}; -- 2.34.1