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Sun, 28 Jun 2026 07:39:16 -0700 (PDT) Received: from hu-vdadhani-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c7c4ca240sm39300591eec.4.2026.06.28.07.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2026 07:39:16 -0700 (PDT) From: Viken Dadhaniya Date: Sun, 28 Jun 2026 20:09:04 +0530 Subject: [PATCH v1 1/3] dt-bindings: i2c: Add Qualcomm I2C slave controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260628-i2c-qcom-slave-v1-1-8b0a5c01f9f6@oss.qualcomm.com> References: <20260628-i2c-qcom-slave-v1-0-8b0a5c01f9f6@oss.qualcomm.com> In-Reply-To: <20260628-i2c-qcom-slave-v1-0-8b0a5c01f9f6@oss.qualcomm.com> To: Mukesh Kumar Savaliya , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Viken Dadhaniya X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; 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The block operates only as an I2C slave and supports FIFO/PIO transfers, so it needs a binding separate from Qualcomm I2C master controllers. Document the MMIO region, interrupt, XO and AHB clocks, interconnect path, and the 7-bit slave address needed to describe the controller in device tree. Use the 'qcom,slave-addr' property for the slave address because 'reg' describes the controller MMIO range, and this slave-only controller has no child node where an I2C address can be encoded. Signed-off-by: Viken Dadhaniya --- .../devicetree/bindings/i2c/qcom,i2c-slave.yaml | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-slave.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-slave.yaml new file mode 100644 index 000000000000..3096ff2e62d3 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-slave.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/qcom,i2c-slave.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm I2C Slave Controller + +maintainers: + - Mukesh Kumar Savaliya + - Viken Dadhaniya + +description: + The Qualcomm I2C slave controller is a dedicated hardware IP found on + Qualcomm SoCs that operates exclusively as an I2C slave device on the bus. + It supports FIFO (PIO) mode for data transfer and does not function as an + I2C master. + +properties: + compatible: + const: qcom,i2c-slave + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: XO clock for I2C slave + - description: AHB clock for I2C slave + + clock-names: + items: + - const: sm_bus_xo_clk + - const: sm_bus_ahb_clk + + qcom,slave-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The 7-bit I2C slave address programmed into the controller's device + address register. This controller operates exclusively as an I2C slave + and has no child nodes, so the standard 'reg' property cannot be used + to convey the I2C address (it is already used for the MMIO register + range). The address is configurable at runtime via a hardware register. + minimum: 0x08 + maximum: 0x77 + + interconnects: + maxItems: 1 + + interconnect-names: + const: i2c-slave-config + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - qcom,slave-addr + - interconnects + - interconnect-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + i2c-slave@88ca000 { + compatible = "qcom,i2c-slave"; + reg = <0x88ca000 0x64>; + clocks = <&gcc GCC_SM_BUS_XO_CLK>, <&gcc GCC_SM_BUS_AHB_CLK>; + clock-names = "sm_bus_xo_clk", "sm_bus_ahb_clk"; + interrupts = ; + qcom,slave-addr = <0x30>; + + interconnect-names = "i2c-slave-config"; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SMBUS_CFG 0>; + }; +... -- 2.34.1