From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 106E3346795 for ; Mon, 29 Jun 2026 07:36:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782718575; cv=none; b=PLBhYjq1MRolmTD678H1g+8zMX6kwewZd6zPsrkjwPa+B1w7I8KC8MgzlgGlcQlL+SQ/liGpA+tmEQE9s+lHp7RLIZbiNPy+6wwiQxEVWiIb9nGjRTrtZMlIcZ6MMG1fzR3QCn2b1O0Uv0Wxsay/qEFQoLD8D7H1b1IlLATAAJM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782718575; c=relaxed/simple; bh=xm5CxsUKMbCzRIh76JFDuGswHLuECFh0jFoVKUFTh+k=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=cXL8TROVovT0PnfxInkRNF6kPtUrKmcCGtAPeheQ6YErshz2MQUEfxZ/ygNxmUdafy09tHhtPQ7gPr1/TRFURLaIsYtnURDzVk1d8r7yiJW32cTT+E13duORNujk4OK2n1thC4E2U2ZgFoK87qsPsrPiNUgUXXJ9yMCCu2T/NOw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=V06HOYaR; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MTUJOscy; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="V06HOYaR"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MTUJOscy" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65T6rFUv2135817 for ; Mon, 29 Jun 2026 07:36:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=z/SbcSMIk/FEwys9cVxncR QPP6glnhqNOthgYFbVrVc=; b=V06HOYaRQE9YZVlqFnyNoDqHQJfYRyiHUmcHZx ULYKQ+nl5WXHciuyvjoi10goyspXRcj8cpJKofGRRa1td0o8fx1eFnPrt8B1CVmP vK3rMvVh5srYpsojOYiziIp4GeaYQxTEzhrwSZSb20yMRASPXWqe/iyHcWcUeBl8 xx9Ws6b2Pp4CQHZ2mRvJTsvkla5vIKVYlLz41bnzGlRyIt6sikxO+yAeRw0GIy6w KEL9W+dLNeOMzceYp4LC4wO+Mk6yZ1ERPpMCojiQ7kuAW2bL7hllqEsiGQ3E2ZNy JqtkDAkIb9mcutRwsDpRYhoR166DzOr54t66v1ONtQ+F8Gmw== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f26tun6dh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Jun 2026 07:36:06 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2c9d8549d55so6534695ad.0 for ; Mon, 29 Jun 2026 00:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782718566; x=1783323366; darn=vger.kernel.org; h=cc:to:content-transfer-encoding:mime-version:message-id:date :subject:from:from:to:cc:subject:date:message-id:reply-to; bh=z/SbcSMIk/FEwys9cVxncRQPP6glnhqNOthgYFbVrVc=; b=MTUJOscyxkdHkHO7mQbPC/RDZdlCBPCQjo133T0tkvdSN1pOn7ga1/Z97m8TAFMqEi BKpNpfs6H6bUmwG+5W0Kj9xeetz9trgzCf9s4bFCvl5oW0O5cla3f23ZPb6KT6IKDTic QJ/sB0JWSUce2z10nG3iyMWUcESer61MN6UMzZGKL8w9L3F79HFWrf/a4YpbIRdJ0nbT AmxqYq33Qa+KAfobBtQVofAwadA1/k/dZ5hv/XW4y5hQrKLxkIy171pokWZiaxCoJukp hVWeDd7eRWhtkQ0x6fS0oYPZWJI5OICh9RY2u1g0OI/tGP3WbrIP93UZX4i97N/nnfja L1QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782718566; x=1783323366; h=cc:to:content-transfer-encoding:mime-version:message-id:date :subject:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=z/SbcSMIk/FEwys9cVxncRQPP6glnhqNOthgYFbVrVc=; b=PRGar20Vcus+gpssDOg2xVAV9HLobBNo3TamlzSAUoYMRJcJjorA7g6/oBaOppRP02 LgUYId5jxt4zTmfmRqh3BT8y3UbnPTwrv2rmU0vomwhWYMSXGqRj/QxsQvbA5k7Zv6Gg N59/gXOvo/lTIcoYHZ3UY9w7NDL5+co8RyK/ERyg4Hq/HIIJBZVup+ZZkdHROm22nJMd JOTFQXzB7z7vXMlBj9vmpRtkiKBE5nmi338DnVeFFzIYFvLbySEIUBjvsVuMRGYJ4tdX 5kHaLYmRcsP5CJCXL3gVcpTzC2+peR6s8+xo6Vexd/brck0rNkh3UMmJ0sKnL6pM6OPg w1DA== X-Forwarded-Encrypted: i=1; AHgh+RodGLkrCensNZ10JRt91CfSlSbXLl/5ZbEpvhKxgI+RFEJzfDV3hUcBmq13P93Zp9/vw5CF9A8RCnbKzgw=@vger.kernel.org X-Gm-Message-State: AOJu0YyTfgZMjoR37/SnxcSXWI79Nd736pTxEtBmt+WsPRlFYQ26SI7H rYoly/X9GY3Sc7Txfwm2qQ2eosUUKr16RWkf1onZhGsMgLI0TnqST0/XmMP08y3TO/s6xvohLDx /gQ3W84OeuaO3NsrP21ifD7qnbtYKJUpDC6D7bhWoMk1DMYjg532yi/bbTK7r1JXm4lY= X-Gm-Gg: AfdE7cnQfsggx++MThyT80ilavhghTQXbJqEP2lQFnbqEFEtgQsBvSlKzMqzexaE2YN 3hajRxDbrLCTPDgXrcGMZTSuyu05xAMfnxji9iKw1dGtbvVu3EM8k7AjBqRaSflh9ShWrRHhK16 n+JU6ZOwEvFDQBjp6pVVbKRuTdSnd1CTdmTdYMoYLCF15tlp4DEbBPZJ6HVQ+1hfYtBThiXHkP3 Qt8PAQ3lNoCotqoUXR04Bh0wwT3YOac0W3OGqw6t71c/TAciXjyMpP7QiYgfhHxfKdoi/wvX763 zY8kbod2svkjAjfh4pMLcFUlF6ndge/mfbhGOtNqBMcBl0sojl46nRtYt7ezOsxMn+WpLyln5YQ fPkuujN3PeOwRYaqXY+cUNcuDPLo3h5Yf0kbuhmZ0F+4f X-Received: by 2002:a17:90a:d450:b0:37f:9ce0:af32 with SMTP id 98e67ed59e1d1-37f9ce0af84mr6821370a91.29.1782718565530; Mon, 29 Jun 2026 00:36:05 -0700 (PDT) X-Received: by 2002:a17:90a:d450:b0:37f:9ce0:af32 with SMTP id 98e67ed59e1d1-37f9ce0af84mr6821352a91.29.1782718564958; Mon, 29 Jun 2026 00:36:04 -0700 (PDT) Received: from hu-kuldsing-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-37fa9629f8fsm4537979a91.8.2026.06.29.00.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 00:36:04 -0700 (PDT) From: Kuldeep Singh Subject: [PATCH v8 0/3] Enable sdhc inline crypto engine for kodiak and monaco Date: Mon, 29 Jun 2026 13:05:30 +0530 Message-Id: <20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAEIgQmoC/02MywrCMBBFf6VkbcI0JKW68j9EShqnNsU8zLQil P67qW7cXDhwz1kZYXZI7FStLOPLkYuhQHuomB1NuCN3t8JMgmygkUfuLHbove1oSSnmmfdS2Vb ZXoNWrGgp4+De3+Tl+mNa+gntvHf2x5Cj5/OY0fyloQVVNxqEVrUGyWseELOZBMXgzpFIPBfzs NF7UYZt2weKnOuluwAAAA== X-Change-ID: 20260629-ice_emmc_support-b24c84cb5054 To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neeraj Soni , Abhinaba Rakshit , Krzysztof Kozlowski , Kuldeep Singh , Abel Vesa X-Mailer: b4 0.15.2 X-Proofpoint-GUID: FCOj0qUaCYmBA_DJIUszABc0bKF81p2S X-Authority-Analysis: v=2.4 cv=A8Rc+aWG c=1 sm=1 tr=0 ts=6a422066 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=xtQGQhj0aSk4Y_6bxbsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: FCOj0qUaCYmBA_DJIUszABc0bKF81p2S X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA2MSBTYWx0ZWRfX7UEP5EeULDFJ A3XtbaXWXui1uRkGnQ5YZhjElWE3L1BEzSsTH+8BhuKCEVH67j5rqSSUNWxoXd+3CwL/FIO6cOT P02mWJJJ9soInhu71KlYZgX5g5y4bvu120KjmdrQZXKI630pkYkoYNmK9ALUhsqcwQ6Okz6o8lF +lXMWRFqANMIqEJm7FY1umeP4Hwgu42eYR9L+mSGpLHgSvwzANL0B6hK5iaRV9NNjX96qlvufrw lWvk+SJc7wnSDfAiVh4KEa87NsQnK8YWx9RO8dja84aEpwATwZUHpPOePdf32hzjFp8gLAk5DR+ 3NjSYXW8fU2EK2/Gl1oUr666S0T+u+V2oo9FlTaGyjz9LuXcBMuHGMMePRogvlyFY3uAsqDwiG5 OFjVuzTrwLY0OaXbczWAw8/pVH50nBPtgsDYLzl2RAvoYekkLOf7Uo8ztcJlOzLYbGvQebkP8VD iD9C99rjpDB+rNl08mg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA2MSBTYWx0ZWRfX1ValXAEcI1rn lb1Aj0sq5+1T9sqGIxBGQJ6DHPI1meDQJ7d4eSIzZy5txS1bpVUjG6QAccoaOngNsqdLxPgOXyI n9diaK/ZexBQiwvb+8bwBnnCWCQjQP4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290061 The series is combination of below 2 series sent in past. Since, both need to be picked together, combine them and send as one series. Konrad and Krzysztof, request to review series again as I've made minor changes only to this series. - https://lore.kernel.org/lkml/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com/ - https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/ Document and wire the SDHCI to ICE relationship on Qualcomm platforms where ICE is modelled as a dedicated DT node. This series: - adds the qcom,ice phandle to the SDHCI binding and enforces the qcom,ice vs embedded-reg modelling rule, - enables ICE for kodiak and monaco by wiring SDHC to the dedicated ICE node, - adds interface clock and power-domain requirements for the ICE node in affected DTS files. The ICE node is kept disabled at SoC .dtsi level and enabled in board .dts files where the corresponding SDHC node is enabled. This keeps the SoC description reusable and avoids enabling ICE on boards that do not use that SDHC instance. How this series was tested: - make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- \ DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml \ dt_binding_check - make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- CHECK_DTBS=y \ qcom/monaco-arduino-monza.dtb qcom/monaco-evk.dtb \ qcom/qcm6490-fairphone-fp5.dtb qcom/qcm6490-idp.dtb \ qcom/qcm6490-particle-tachyon.dtb qcom/qcm6490-shift-otter.dtb \ qcom/qcs6490-radxa-dragon-q6a.dtb qcom/qcs6490-rb3gen2.dtb \ qcom/qcs6490-thundercomm-minipc-g1iot.dtb \ qcom/qcs6490-thundercomm-rubikpi3.dtb qcom/qcs8300-ride.dtb \ qcom/sc7280-crd-r3.dtb qcom/sc7280-herobrine-crd-pro.dtb \ qcom/sc7280-herobrine-crd.dtb qcom/sc7280-herobrine-evoker-lte.dtb \ qcom/sc7280-herobrine-evoker.dtb qcom/sc7280-herobrine-herobrine-r1.dtb \ qcom/sc7280-herobrine-villager-r0.dtb \ qcom/sc7280-herobrine-villager-r1-lte.dtb \ qcom/sc7280-herobrine-villager-r1.dtb \ qcom/sc7280-herobrine-zombie-lte.dtb \ qcom/sc7280-herobrine-zombie-nvme-lte.dtb \ qcom/sc7280-herobrine-zombie-nvme.dtb qcom/sc7280-herobrine-zombie.dtb \ qcom/sc7280-idp.dtb qcom/sc7280-idp2.dtb \ qcom/sm7325-motorola-dubai.dtb qcom/sm7325-nothing-spacewar.dtb Changes in v8: - Added iface clock, clock-names, power-domain and disabled status in kodiak and monaco ICE nodes. - Enabled ICE in board DTS files where SDHC is enabled while keeping SoC ICE nodes disabled by default. - Updated trailers to reflect co-development and sender sign-off order. - Revalidated with dt_binding_check and CHECK_DTBS for all impacted DTS. - Link to v7: https://lore.kernel.org/all/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com/ Changes in v7: - Rebased on latest linux-next (sdhci-msm.yaml renamed to qcom,sdhci-msm.yaml). - Added links for previous versions. - Link to v6: https://lore.kernel.org/all/20260310113557.348502-1-neeraj.soni@oss.qualcomm.com/ Changes in v6: - Wrapped commit message for patch (1/3) as per Linux coding guidelines. - Signed off the patch (3/3). - Link to v5: https://lore.kernel.org/all/20260306093332.4193993-1-neeraj.soni@oss.qualcomm.com/ Changes in v5: - Updated the constraint for SDHCI 'v4' vs rest to reflect the 'qcom,ice' constraint. - Link to v4: https://lore.kernel.org/all/20260217052526.2335759-1-neeraj.soni@oss.qualcomm.com/ Changes in v4: - Added a new patch (3/3) for device tree changes for Monaco SoC. - Updated commit subject of cover letter to reflect "monaco". - Removed the text description of constraints from "description:" for "qcom,ice" and wrapped the code. - Corrected the schema code to reflect the constraint of "qcom,ice" usage properly. - Link to v3: https://lore.kernel.org/all/20260206112053.3287756-1-neeraj.soni@oss.qualcomm.com/ Changes in v3: - Described the purpose for phandle in "description:" for "qcom,ice". - Re-added the "if: required:" description for "qcom,ice" with proper encoding. - Corrected the uppercase for base address and reg address space for ICE DT node. - Link to v2: https://lore.kernel.org/all/20260114094848.3790487-1-neeraj.soni@oss.qualcomm.com/ Changes in v2: - Removed the "if: required:" description for "qcom,ice" dt-binding as the ICE node is optional. - Corrected the ICE dt node entry according to the dt-binding description. - Added test details. - Link to v1: https://lore.kernel.org/all/20251124111914.3187803-1-neeraj.soni@oss.qualcomm.com/ Changes in v1: - Updated the dt-binding for ICE node. - Added the dt node for ICE for kodiak. --- Neeraj Soni (3): dt-bindings: mmc: sdhci-msm: add ICE phandle arm64: dts: qcom: kodiak: enable inline crypto engine for SDHC arm64: dts: qcom: monaco: enable inline crypto engine for SDHC .../devicetree/bindings/mmc/qcom,sdhci-msm.yaml | 95 +++++++++++++++------- arch/arm64/boot/dts/qcom/kodiak.dtsi | 14 ++++ arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 + arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi | 4 + arch/arm64/boot/dts/qcom/monaco.dtsi | 14 ++++ arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 4 + .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 + arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 + arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 4 + .../boot/dts/qcom/sc7280-herobrine-evoker.dtsi | 4 + .../dts/qcom/sc7280-herobrine-herobrine-r1.dts | 4 + .../boot/dts/qcom/sc7280-herobrine-villager.dtsi | 4 + .../boot/dts/qcom/sc7280-herobrine-zombie.dtsi | 4 + arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 + 14 files changed, 139 insertions(+), 28 deletions(-) --- base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43 change-id: 20260629-ice_emmc_support-b24c84cb5054 Best regards, -- Kuldeep Singh