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Mon, 29 Jun 2026 00:36:10 -0700 (PDT) Received: from hu-kuldsing-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-37fa9629f8fsm4537979a91.8.2026.06.29.00.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 00:36:09 -0700 (PDT) From: Kuldeep Singh Date: Mon, 29 Jun 2026 13:05:31 +0530 Subject: [PATCH v8 1/3] dt-bindings: mmc: sdhci-msm: add ICE phandle Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260629-ice_emmc_support-v8-1-1a26e1717b85@oss.qualcomm.com> References: <20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com> In-Reply-To: <20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neeraj Soni , Abhinaba Rakshit , Krzysztof Kozlowski , Kuldeep Singh , Abel Vesa X-Mailer: b4 0.15.2 X-Authority-Analysis: v=2.4 cv=F+FnsKhN c=1 sm=1 tr=0 ts=6a42206b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Hwb5qPKBi1csoFV4ZQQA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: EwyUnanww22UnJAvBZZkOVQIWEV1uFBk X-Proofpoint-ORIG-GUID: EwyUnanww22UnJAvBZZkOVQIWEV1uFBk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA2MSBTYWx0ZWRfX55JhWxzZ+JBx kiW4F3+NctiDt+gMIj8WSCk75aoUm3ma5kNemi7A3yJiWR7j0sqjlMxNif+7tYZRP/9Jp1C2e6l 6DYnoJicIqVzSLpegcibr2aLUF0odvEv+E5+8pTRVrs3Z9H6sagQE4y9Bn0QSolgV79V6IbGzIm HxIaGf3hZghLtXJn/DIGiXa+cXN+MjdcGYGfiIr0ozknA7TdV+MdjT37etHIF6qg12PMyL9dmRI 6rr55wxFAhIDikqG6QWHCT/sMlP8u8le428NTAbyVs0n5c49E0VUYqhuA1vSOw013iS652x1Ywx KXqY5mp5MCGO6l4789VVDu+5CMshZkL01tipnkP90J80NXopaI4tuOMVGs9pzyoRHRR1QF7mIWI qdbt/fNkMJMw+FcEm4kShsDqk/O0EBMXZGDVhTHWK1o3eziZ0r/NdKfsPz7aPjYSLhx/GAFF/7D ye4P/6q87LUsC9FMAbA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA2MSBTYWx0ZWRfX/T/7s8VB704R 81uhXURzG/tPGPSSWHGoW7S5HxZlUod2a3JC2VeH9iX9ElY08mkG5tRnATTAplngwjihFbH4BJs LFKK8lXMAj89LDO7LoSzjIxuuG7eDDA= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290061 From: Neeraj Soni On newer Qualcomm SoCs (starting with sc7280/kodiak), ICE is modelled as a dedicated DT node. Add the optional qcom,ice phandle to reference that node from the SDHCI controller. When qcom,ice is present, disallow an embedded ICE register region in the SDHCI node to avoid double modelling. Older SoCs without qcom,ice remain valid. Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Abhinaba Rakshit Signed-off-by: Abhinaba Rakshit Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neeraj Soni Signed-off-by: Kuldeep Singh --- .../devicetree/bindings/mmc/qcom,sdhci-msm.yaml | 95 +++++++++++++++------- 1 file changed, 67 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml index bd558a11b792..b3fcc1673c10 100644 --- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml @@ -145,6 +145,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the Inline Crypto Engine (ICE) hardware block for this controller. + iommus: minItems: 1 maxItems: 8 @@ -198,35 +203,69 @@ allOf: enum: - qcom,sdhci-msm-v4 then: - properties: - reg: - minItems: 2 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 2 - items: - - const: hc - - const: core - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + else: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice else: - properties: - reg: - minItems: 1 - items: - - description: Host controller register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 1 - items: - - const: hc - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice unevaluatedProperties: false -- 2.34.1