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Mon, 29 Jun 2026 00:36:19 -0700 (PDT) Received: from hu-kuldsing-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-37fa9629f8fsm4537979a91.8.2026.06.29.00.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 00:36:19 -0700 (PDT) From: Kuldeep Singh Date: Mon, 29 Jun 2026 13:05:33 +0530 Subject: [PATCH v8 3/3] arm64: dts: qcom: monaco: enable inline crypto engine for SDHC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260629-ice_emmc_support-v8-3-1a26e1717b85@oss.qualcomm.com> References: <20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com> In-Reply-To: <20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neeraj Soni , Kuldeep Singh X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA2MSBTYWx0ZWRfX0bGgY//b9nKY 5VUvaSVCCXQPfzjEywUqtpkLEiKQItkx76COuy3RHJ9isrMtgujurKBgqg1arzbOUT38khEcVGL BSIWfhFakCTaSm9Fvx5KDH9F3aUqwRU7qxX1efD/3NwuiDcXZbaqAnj5wZ4NTy1yqHKCvY9jpM9 Y6R8nOglwHnBcEgcIR1H5T6pKaJYkQQZua/5GZ/JYGYG1jyB+v3/3zrhczS/BMJxeE/MjtSVnVo 0jd/y3PSG0Y73aJ/CB2ypCZ9V27plWICR5fDY8Msf5rmnUWuAgttzV3JqIQH/nLMJjUtclTKvq1 szX+n2V7WrQt8gTn8r2QalHYcv3cynQcMj98ggd1JgwijuiZZCZaKm9TRQTbEXu8O3gsSEEXwtV lVy15CbQfK1dPjBIc8aR1Kk42ePVEGc/OP4YaMIup/hZQ9nlTPu/oAFx5SS77h6h3Twz+20HTuh xSjMvD7Z2GeQVX0S8kQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA2MSBTYWx0ZWRfX9sr1u9FrAatR xFIrxHtIPlo3DJ00fzcXgOmOW4pbG5c1mlu6tGfezB6O1ULva3iW8dot2UTcAAXHYD7CsuNY18x GflPCaVGnIVdoatuS64PSA1EQcTS0tI= X-Proofpoint-GUID: 6D726Fzay3emwK5EvWIJeLnHZ6u8AQZC X-Proofpoint-ORIG-GUID: 6D726Fzay3emwK5EvWIJeLnHZ6u8AQZC X-Authority-Analysis: v=2.4 cv=Fe4HAp+6 c=1 sm=1 tr=0 ts=6a422074 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=1TJM2g-zu_yJeCZsWRQA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290061 From: Neeraj Soni Add the dedicated ICE node for monaco and reference it from the SDHC controller via qcom,ice. Keep the ICE node disabled by default in monaco.dtsi and enable it in board DTS files where the corresponding SDHC node is enabled. Signed-off-by: Neeraj Soni Co-developed-by: Kuldeep Singh Signed-off-by: Kuldeep Singh --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 ++++ arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++++ 4 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 9d17ef7d2caf..2c7d6ebc54fa 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -705,6 +705,10 @@ &sdhc_1 { status = "okay"; }; +&sdhc_ice { + status = "okay"; +}; + &serdes0 { phy-supply = <&vreg_l4a>; diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi index 9b5ed55939b8..62c6f45025c1 100644 --- a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -282,6 +282,10 @@ &sdhc_1 { status = "okay"; }; +&sdhc_ice { + status = "okay"; +}; + /* Ethernet/SGMII */ &serdes0 { phy-supply = <&vreg_l5a>; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index e4c8466f941b..71f4bb164ec3 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4835,6 +4835,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, supports-cqe; dma-coherent; + qcom,ice = <&sdhc_ice>; + mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; @@ -4867,6 +4869,18 @@ opp-384000000 { }; }; + sdhc_ice: crypto@87c8000 { + compatible = "qcom,qcs8300-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x087c8000 0x0 0x18000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&rpmhpd RPMHPD_CX>; + status = "disabled"; + }; + usb_1_hsphy: phy@8904000 { compatible = "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index e9a8553a8d82..58c4a328bd3d 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -726,6 +726,10 @@ &sdhc_1 { status = "okay"; }; +&sdhc_ice { + status = "okay"; +}; + &tlmm { bt_en_state: bt-en-state { pins = "gpio55"; -- 2.34.1