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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9260079070bsm2143165885a.40.2026.06.29.07.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 07:15:56 -0700 (PDT) From: Yongxing Mou To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Dmitry Baryshkov Subject: [PATCH RESEND v5 10/25] drm/msm/dp: Always program MST_FIFO_CONSTANT_FILL for MST use cases Date: Mon, 29 Jun 2026 22:14:31 +0800 Message-ID: <20260629-msm-dp-mst-v5-10-2ed6aee1867a@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> References: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782742144; l=2539; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=NN3ZQ7RQKQ4IPtPV9Psg0vrIOb4voIVZosbAYDy6STY=; b=Wo0n4ZkKEwYBX70C4SIo6eYGpFXBnBHwd+EEq4+mLkMkNwPLRgJcqXZ7YtksKBSTHl7xTTCQ5 2ZcEikVCzbtCuI/H7RE4pOEcKodV8H9ERY/4aL3o9tkxJTKyhvtzGJi X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 0e5I1jRVBoCE417CQG0CoSU7OMERnnai X-Authority-Analysis: v=2.4 cv=Z4Hc2nRA c=1 sm=1 tr=0 ts=6a427e1e cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=_o_Q1azn2oY438DeJ5EA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDExOCBTYWx0ZWRfX5mzxMLcDlx35 93etJYBfIjM36b0ETWIC9lI9OeBGph8z5kO7BijnwG++u9Jc5nDwc8GW7v3ByH2k5cGak76gXfC AZZ+nyWjLIfECYIPNNsbPcW3g+pKmJM= X-Proofpoint-GUID: 0e5I1jRVBoCE417CQG0CoSU7OMERnnai X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDExOCBTYWx0ZWRfX4TlB2XWSVXZH jHoYpD0rnCVbnKtg7y6IoWnISH1UV2DhFFv2Ur/YQFAw6I28Yen0jI+jmEapjmMwUAUZ3l2GW9f 45xzyIkYSw2lTU5f2oGGE68cKKq7ck9PVr6vOFSuteQra4pT4fvxLGnwQO2Vba9Ex0JYn1Tmyoy pgdF876l76yHiOUCWFWj29t+5EdXVWNDMT+2VdM8DuMJEuhzXSPnAwptfmwWGmnR4QDtvUmqAar u53JXgju8/ryJkhrPrlb9VfHlTB4DzQAnCmRr8KtL6pDWrL8RE34/GZLH12nM0Ds4Zudn0n6jDj KdPaodapETYZnV0fT5O+Lo+tCmVN1qJvaF+JhENPe3BSxR6e62tJ/fCJLHzlA+mBIKuYnapkgUC 5OcBeIsMN8RB3px6oIgfgds3QWQlKP43YlhuMKcadDErXJgEfcrZq+VrH4k0CBiH/bhgxOvQICR kIX8dsfV+cDBe5qD68A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_03,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290118 From: Abhinav Kumar As per the hardware programming guide, MST_FIFO_CONSTANT_FILL must always be programmed when operating in MST mode. Ensure the register is configured accordingly. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 12 ++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index c4f1a68b1210..80116e19fbbf 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -677,6 +677,8 @@ static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl msm_dp_ctrl_config_misc1_misc0(ctrl, panel); msm_dp_panel_timing_cfg(panel, ctrl->msm_dp_ctrl.wide_bus_en); + + msm_dp_panel_mst_async_fifo(panel, ctrl->mst_active); } /* diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index cbbcc0dbf652..ba5ee2ad8924 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -741,6 +741,18 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) return 0; } +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en) +{ + struct msm_dp_panel_private *panel; + + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + + if (mst_en) + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); + else + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); +} + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, const struct drm_display_mode *adjusted_mode, u32 bpp) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 3e78af9e430d..edc39ee5268e 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -73,6 +73,8 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel); void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp); void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en); + /** * is_link_rate_valid() - validates the link rate * @bw_code: link rate requested by the sink -- 2.43.0