From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C80D7413D95 for ; Mon, 29 Jun 2026 14:16:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782742612; cv=none; b=TK5jJP1IHbDbQbmb8WnXdvCU0S/aNLdHTcLGg4n/N2Xap+8E/6Xt5s/L2ICIQ9cBDtTKHAoErpgPChjnrmrPPQMfv02gWDu4xsw7MUPbWLv3FZhxO6rKy/dYgexdFvMc0CYF/Wr+lueG8k/JugcjMeafof62N5LrZZ7u5+K6TB8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782742612; c=relaxed/simple; bh=ZmA6j9PaSgiCKIx18GfrmSXgrNCTuY6lHFe4jcnsXM8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=u+SYBPILJngOKYZIyIHKxgzcmeHhHGYYWt0BB1x3AWv6I1kCMfOFPCF7O2CNbyOJQDTFT1IRgS/PZkmsNWtdYvl1EhdO5hqnEGHEVsA/CqCxP+uNdN0NP8C8nbBVYO9eoZID2pHOxYY+69VP/nfB9VvfzJlyHsaYK09FY1gpF2M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JXFiJjnC; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=YntpBC0N; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JXFiJjnC"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="YntpBC0N" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65TAT7HY2627945 for ; Mon, 29 Jun 2026 14:16:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= RTRODGoRdiTbi9v1uwQEXTif90CmJA2jnvlNqKTiqQE=; b=JXFiJjnCoOH0JiAW fbz6LJ4Rq7zsariBN2F26SwD9Jk+OQX4C2EIr7YTPWMwejMSXEyD4wXGdLXTnCqS FP0DVLAtuVChwSTE3JzNP5xkha3+fVDyB2rbqmqHmehljZE3MP7xcKq0odvVl8eJ Zk07D2IER2QxZ7NQIVabE3bJoUlKOktW5HcBCUmeUZq4JAvdMLwWxQy2r7I4oXdX g2/XnR2fdrJRH3LwuXzdQoDALUq1hoGZeiJQlxDmxEZNBR420HZ/5txmRH/t+hWP rj0koHNwRSscV5QP0IWwSHhD5vX6NE4bEQ/IXIY2CWNZtgokQhAhz5viADKDEhmZ iM3zMA== Received: from mail-vs1-f72.google.com (mail-vs1-f72.google.com [209.85.217.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f3nbgs936-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Jun 2026 14:16:49 +0000 (GMT) Received: by mail-vs1-f72.google.com with SMTP id ada2fe7eead31-737bcdb48d2so948585137.2 for ; Mon, 29 Jun 2026 07:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782742609; x=1783347409; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RTRODGoRdiTbi9v1uwQEXTif90CmJA2jnvlNqKTiqQE=; b=YntpBC0NrCj0cxtL114FZnOlZGh6OFzcdeG3iV4yEj6VpBRNmIi9F7RfSuFu8L+J6P lC0O+gnjluL9hTfBJwIPIQ87fN7V5ctiIGItSwS561UjsecR+LQ6fb67TXjWkqViMP98 BzaTrq8pQf9JEE7YQnmREFQvIkIauG8rhbfNFLynM4rgR1smKhMA7iHnM1h5UY06Ql2y 1iG/TXL+5UQuyRZj6/mgyWPOhLNOJTsbAcIcczzoARzTRTE9p43lOTCd9EtxleVSwaDl UFKDhrkMbBJsyVRs75FIkxX95wdKuqg/WcnkNfNClDJ1MBiltqCRCLzUUkf2LHeH1c+m BFpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782742609; x=1783347409; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=RTRODGoRdiTbi9v1uwQEXTif90CmJA2jnvlNqKTiqQE=; b=eeCbYMeJmaLaw3PYwceA1VfqchxmEvq82Z5WI1r93tiIHCa2gF/sNziY5qnEuqaSEs QGXZnBOA6yCcbDgbWD12TUuWwuSeFoisl7swgFJv/rjtwq1FtG4/vlXnbRAHD4cuWeGf tEydMkLUKlVJE+Cv6gMN8qK0YAXiRDPq0AKqe75iOkSPrsiNulvWp3SIUYoWiIZxTuu8 v/wWtx6PVKPl1rGm/QunmAFyI4ygWkmmympFobxpnvhB+GT33jDFgfu03PqbXDc+oiDz +KHXZvMDhBotUaDXEwX3bFj07zhHCQ9lvk0VnZXQlV/3T10KAKJoE/BlnzGayzp5LaO9 c1CQ== X-Forwarded-Encrypted: i=1; AHgh+Rp6YH6GUKthPJn9nxTBBZNpCxFnKTsRQGKg9rSiO+aSdvtuacaNRZV3ggggaeCxWjaNYOoqkL2ODu28SKk=@vger.kernel.org X-Gm-Message-State: AOJu0YyfbVOzmngQihvvvZnP3yHMIZ+5m+R/s8boFEZStAFzlVpMiXr5 qIASM2PHbZ/YPC3+DBBeSc/4koEFI71DST+Mf1035LaJMPo2smc91cWky84bnVoNZDhTttEYj8h dKdREYFAo6XiFS5hHTb0Gvi5iPkqgJJekk7HafIn7bMQsunmwEahlii7tKjvRbnQDhP4= X-Gm-Gg: AfdE7cm5C/xn0aeCpvaWGwiWskFYstvpcaBTzdJ6hWtO+4ilbxfJUJeh51SNuz/uzZY GFINmbnJB9bIAh7/E93DMD70mFAsocJC1xmXSTppd3FU9gDc5ALOLMzZRligrm69R00dLl44fPs 81rC3oxXeYYQi1iTTfERvP1Oy0jqFKsz0KN1LHGYbgWVpVvqjs+XOYg/iakgQHBI1d+0CCJXd19 tNoH8WHV8/wjYbKb3tCynXUjonbQ92CvpZ/XO07upbcrU5uj050Q9BTvws3betYhBG+1+nIWF5E JrzUjGJ6FcDh+lHX/B7lDDmjv2C1hU2yPsduQAfjmfvl66vKCbzkB0noplz+jrU0pu/jOJnqydZ dFhV1GRMQUsqLH3rXUzG9agIFRn3BlD3EOi4NBZYtYp+RmT2ZfizggGtG/hJTfm8NS5NRBA== X-Received: by 2002:a05:6102:6c2:b0:738:5e0:b40e with SMTP id ada2fe7eead31-73805e0c206mr2379947137.27.1782742608444; Mon, 29 Jun 2026 07:16:48 -0700 (PDT) X-Received: by 2002:a05:6102:6c2:b0:738:5e0:b40e with SMTP id ada2fe7eead31-73805e0c206mr2378903137.27.1782742602665; Mon, 29 Jun 2026 07:16:42 -0700 (PDT) Received: from yongmou2.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9260079070bsm2143165885a.40.2026.06.29.07.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 07:16:42 -0700 (PDT) From: Yongxing Mou To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar Subject: [PATCH RESEND v5 19/25] drm/msm/dp: initialize dp_mst module for each DP MST controller Date: Mon, 29 Jun 2026 22:14:40 +0800 Message-ID: <20260629-msm-dp-mst-v5-19-2ed6aee1867a@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> References: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782742144; l=7456; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=6XyUS6qRZs5X6/pKt4qoYuSBISthOP33nj+/4w99iLA=; b=Fo5ChQ3bWGgWBF0ZWi5k8jQ2i+CvNMg3W9DPQMRLKcyjDMZpjLyydl74DKrpXMWWhsVjDASs/ ypflVn3ZpTvCDzXJiqZjye7acqdpx64YLx7BP+5FjeNxGLgIk8QVfet X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: oATOezfwP3wGMkdmOBuucfJydwZuRMga X-Authority-Analysis: v=2.4 cv=Z4Hc2nRA c=1 sm=1 tr=0 ts=6a427e51 cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=Tb4r1nT5KeEeR2f--GEA:9 a=QEXdDO2ut3YA:10 a=-aSRE8QhW-JAV6biHavz:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDExOCBTYWx0ZWRfXygmjR+ZVsxyf OrGrEV44l23igNkooMFm9shMlx63H8y9qAoMO8XSurCH641n6WFp0lb6NcLRCWyyz7NzhmQxRl5 v84k61oEuOax0z6OHvA2VAtv/fnxkFY= X-Proofpoint-GUID: oATOezfwP3wGMkdmOBuucfJydwZuRMga X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDExOCBTYWx0ZWRfX6vKUOiA7IDXe OMCDFkL7MdWiqosohorqyCUPdlZbFyk8Su9ONnai+liLCXl0pjgXayEd65pOlQZ/B9TSG+JbRZq RbUJg3xOe+sdkdbtrMoCyQ1aoLTp1iIvnBxhqcljBHBPirRcn2unh43iivGp4lkKs4nQEL6vUnb DJsuAzPn6aQnbQbIf39bvB6qOCdSpBJmgUPJ5MK8ABTK7MW7A3cmhvTYKJ3tT6NVUkfaQDvV7Fp 5g0wgXwAEOPObskNYzjhtumrYXft2TEPnrQWiMDe9jP6HKh4w4no4XLxJPMYcSsqPg9vwNjUZE0 /7ND1Pprd6bAiscVgqtREO7wf3QoMPaQYLZX60GMrVEUVWSwwzsuAxGebLFlyC61D8Yp/Y5rGKm 1gf+fN0g0rXxPV8HMJRORF6zU6vrOjztt2qn4/7pi0Jq+7cx9CnBhPTh6GW5Fmg+ssYPkkVAAPM KDtXbbggsIjXT/S66BA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_03,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290118 From: Abhinav Kumar For each MST capable DP controller, initialize a dp_mst module to manage its DP MST operations. The DP MST module for each controller is the central entity to manage its topology related operations as well as interfacing with the rest of the DP driver. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 ++++ drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ drivers/gpu/drm/msm/dp/dp_mst_drm.c | 60 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 13 +++++++ drivers/gpu/drm/msm/msm_drv.h | 6 ++++ 7 files changed, 107 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index ba45e99be05b..d510be1c173f 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -145,7 +145,8 @@ msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ dp/dp_link.o \ dp/dp_panel.o \ dp/dp_audio.o \ - dp/dp_utils.o + dp/dp_utils.o \ + dp/dp_mst_drm.o msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 7a00c4094d5c..91d33b432427 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -682,6 +682,12 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, stream_cnt = msm_dp_get_mst_max_stream(priv->kms->dp[i]); if (stream_cnt > 1) { + rc = msm_dp_mst_register(priv->kms->dp[i]); + if (rc) { + DPU_ERROR("dp_mst_init failed for DP, rc = %d\n", rc); + return rc; + } + for (stream_id = 0; stream_id < stream_cnt; stream_id++) { encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); if (IS_ERR(encoder)) { diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index d56ee10ee065..fc9c1e3e57ab 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -28,6 +28,7 @@ #include "dp_drm.h" #include "dp_audio.h" #include "dp_debug.h" +#include "dp_mst_drm.h" static bool psr_enabled = false; module_param(psr_enabled, bool, 0); @@ -351,6 +352,9 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) if (dp->max_stream > 1 && drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd)) msm_dp_display_mst_init(dp); + if (dp->msm_dp_display.mst_active) + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, true); + msm_dp_link_reset_phy_params_vx_px(dp->link); end: @@ -522,6 +526,11 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp) dp->panel->dpcd, dp->panel->downstream_ports); + if (dp->msm_dp_display.mst_active) { + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, false); + dp->msm_dp_display.mst_active = false; + } + /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); @@ -1530,6 +1539,15 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display, struct drm_device *dev, return 0; } +int msm_dp_mst_register(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + + return msm_dp_mst_init(msm_dp_display, dp->max_stream, dp->aux); +} + int msm_dp_display_set_mode_helper(struct msm_dp *msm_dp_display, struct drm_atomic_commit *state, struct drm_encoder *drm_encoder, diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 0464f8941e8d..a185819ec57e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -24,6 +24,8 @@ struct msm_dp { bool is_edp; bool link_ready; + void *msm_dp_mst; + struct msm_dp_audio *msm_dp_audio; bool psr_supported; }; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/dp_mst_drm.c new file mode 100644 index 000000000000..78b8dffe111b --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "dp_mst_drm.h" +#include "dp_panel.h" + +struct msm_dp_mst { + struct drm_dp_mst_topology_mgr mst_mgr; + struct msm_dp *msm_dp; + struct drm_dp_aux *dp_aux; + u32 max_streams; +}; + +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) +{ + struct msm_dp_mst *mst = dp_display->msm_dp_mst; + int rc; + + rc = drm_dp_mst_topology_mgr_set_mst(&mst->mst_mgr, state); + if (rc < 0) { + drm_err(dp_display->drm_dev, + "[MST] failed to set topology mgr state to %d rc:%d\n", state, rc); + } + + drm_dbg_kms(dp_display->drm_dev, "[MST] set_mgr_state state:%d\n", state); + return rc; +} + +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_aux *drm_aux) +{ + struct drm_device *dev = dp_display->drm_dev; + struct msm_dp_mst *mst; + int ret; + + mst = devm_kzalloc(dev->dev, sizeof(*mst), GFP_KERNEL); + if (!mst) + return -ENOMEM; + + mst->msm_dp = dp_display; + mst->max_streams = max_streams; + mst->dp_aux = drm_aux; + + ret = drm_dp_mst_topology_mgr_init(&mst->mst_mgr, dev, + drm_aux, + 16, + max_streams, + dp_display->connector->base.id); + if (ret) { + drm_err(dev, "[MST] topology manager init failed\n"); + return ret; + } + + dp_display->msm_dp_mst = mst; + return 0; +} diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/dp_mst_drm.h new file mode 100644 index 000000000000..5d411529f681 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DP_MST_DRM_H_ +#define _DP_MST_DRM_H_ + +#include "dp_display.h" + +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_aux *drm_aux); +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state); + +#endif /* _DP_MST_DRM_H_ */ diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5fee0b291059..963303079220 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -356,6 +356,7 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); +int msm_dp_mst_register(struct msm_dp *dp_display); #else static inline int __init msm_dp_register(void) { @@ -377,6 +378,11 @@ static inline int msm_dp_get_mst_max_stream(struct msm_dp *dp_display) return -EINVAL; } +static inline int msm_dp_mst_register(struct msm_dp *dp_display) +{ + return -EINVAL; +} + static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) { } -- 2.43.0