From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18BE840E8FF for ; Mon, 29 Jun 2026 14:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782742537; cv=none; b=HG6jLDV9EbbFko+NSE99PExcO5oTf4nvYxxnLsVBS6yD9CL7wQdJlcd1xvcmCbiHIPTbLz2/2bPAmBp1eSarekxfEHEfvY/29TBNSGVq6jHYV7GgMKRHdBBeO+cDDbrHNqIHMUytLLYbOWquOaiGlXDRdABCZRBhs9Qw327M23Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782742537; c=relaxed/simple; bh=HrXfxA0vQxpfmNwi4ljkU3JeEeN7YnnHIMe4CnuWbEw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UoDL+VGyrttxR0RwEI93+qxz/+H3fKrqAuDzDTKzZVCM2BJUrfVVLmRTvTxr+pJ6fw009hQtTveGrjlN1iGblkbWhCrogsNT82H06xvQ3lHWiznJaSy4SrBpQn10Um74gANtDCzac4Ci1ECywfOIAuUx5mrci5aWzlScskC7Kic= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ax4D5Bf2; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=M+vsj4BK; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ax4D5Bf2"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="M+vsj4BK" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65TATAE02627980 for ; Mon, 29 Jun 2026 14:15:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= G/poH3AEjItoo7L5qbK6e3dZL/yIyyfNWIp0WMuk8fQ=; b=ax4D5Bf2/vxx3eIm 6bBczGq0HB5eg1UImixPzrNcR5vczs0kiHokl3duyHpYZxsFz2kyZbvfQsgFZfYL gRooDriO7rBmCicKoqTKSHIMpFb3Ct7br/Oq8tauSCbqIW3WomXFLEpSdpoZD/xO O0de+F3fs1Otkebfu9Kni98f4drypikYaFNjCFjdL9An2uGHkqvDnCjFpQsFPwSH zfFpWwAE5AwZgE7av4R0BUIY1PtV2g6PBPvlMsLVA4Vs18MChPZpQrw5fbAbIAYI djY1cBPo5LdLJPH455+NbRXJjsl1uJllR6qbAK+a45Gmg16RKSYSlHDWd8ttJqo/ K/f71w== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f3nbgs8vv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Jun 2026 14:15:35 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-51c0d6a2f4cso3467791cf.3 for ; Mon, 29 Jun 2026 07:15:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782742534; x=1783347334; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G/poH3AEjItoo7L5qbK6e3dZL/yIyyfNWIp0WMuk8fQ=; b=M+vsj4BKVr96n2u8u9KuZajmBOv96X3r4LCSNO7tFsF3rr74JB6ip84vZrJ/SFP1GW YNN0G7Zuznf+Q+Wnpe260wshhLP4ifxJ94sfHZ/7z7RlKLyKDSwNs7D91TO01WgVR0yM iyJX/HXrKHyttcX0IIim7PfSbjSAThKRnvEbL2qJtmVVkc+qtye9Ireljq+11UrIExPo k7OKKaMbq+jr0PgZNZXmYcUK1I6AzOiWzCKQl8m5c2/6DWSvhaHr79v+7lVF+bnWDzZA bczRN33TsYSEKkU65BGZ1hVE70D7jBgOfPklk4YA+z6M9yN33nUq6iOr1Fs1N1veD2Vc qL1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782742534; x=1783347334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=G/poH3AEjItoo7L5qbK6e3dZL/yIyyfNWIp0WMuk8fQ=; b=BQzu7NFKnSuGcldMzRmgBJVbtFTq1dtEf8PDaxUr735t1Hxvbr5yvBnB1pUI6RXOjU 8+WHUI+50McuBQYDhUH1ne7PEtza/BV9jWTAG8J+yKLH3l1X9fOTdcZvAW/lxsbYA+Xp msEMpDGtkbhX00qpbEebPAr56Z5glBqsIbob6FnD943GWVXgeu2vQunaD4hPdvHiXK0j /a3fhY/6rjQ+da8RGA0yLiFFEWW1a5vvzGxd+RL8pToXvgtXlDwwzJnzBow0MOw2rchr lLWXsqvZcE4J+0yIyRUdOtqyw0OWKxFphgdHSs0HllWRQ8QN0tcctHo7UIU7WdHFPUNd leag== X-Forwarded-Encrypted: i=1; AFNElJ/V6XTcVK1zt7VuxpbO2SNTpV7ZmThNs4+Y0fRqSZnWfJs0e/6tRS2380Zi0p6wBIu56GBExmOm4LR7EqE=@vger.kernel.org X-Gm-Message-State: AOJu0YzxrtCOukILB4rVmDZl8+sxFUR63jDDwMAVWidWsQs5t/2R33KV oF8bX7PdQgmgYdKA7nJsDR0hf52/Ne8gYypXSvyLPQIaBJYaMjntBI2Mo7qUicf0fwd3mIJ1CBq zljWnfSRpyle+ND+e2+Wv7gzLlYXuqDKXFushu/b9OSigw9ye+h8MLBZuk7aBNLVHxc8= X-Gm-Gg: AfdE7ckYZ/uINBDrIHlYsd7GYh7IJSypDbR9dtpH9Y2jtAs0OeNM+S1PVF2FlcoKC4g JwJo2zfPIziicy2jHCiaHuZ74uJVHTKbWhxDgXg1Zl7fJZdo2ghoUQIz0JXtQUmZr3pFUiHtomb CDLyIKBSrxjRXqpyEoJnWVSu3tB5n1pqvYcvVmjdf7o6N24f0CbczYX9FBH/RetnQ29V1yoEp9o UELzOFb5RTMM4S0VyOQay/vyUwsVo2tKLz7bu3bmxxSvWI7uRjYZEHq/8TtE5W9607+rFtsVf/M twjaE/sRmZqePDKDZkwR7GwxYlSxMSWwGAyQOmIeSmDQYoKzUg2qYVdW/2HLKOudeiuN1gqjzHV +ofOsY0QJIvzr17oX/jCmsEYI2otXbcwkFnOrJCd16lrijB1+rlDy4qy13S77JepAnv/lRA== X-Received: by 2002:a05:620a:bce:b0:915:9984:5781 with SMTP id af79cd13be357-9293ccd3e07mr2348340685a.51.1782742534237; Mon, 29 Jun 2026 07:15:34 -0700 (PDT) X-Received: by 2002:a05:620a:bce:b0:915:9984:5781 with SMTP id af79cd13be357-9293ccd3e07mr2348330685a.51.1782742533511; Mon, 29 Jun 2026 07:15:33 -0700 (PDT) Received: from yongmou2.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9260079070bsm2143165885a.40.2026.06.29.07.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 07:15:32 -0700 (PDT) From: Yongxing Mou To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Dmitry Baryshkov Subject: [PATCH RESEND v5 06/25] drm/msm/dp: Add support to enable MST in mainlink control Date: Mon, 29 Jun 2026 22:14:27 +0800 Message-ID: <20260629-msm-dp-mst-v5-6-2ed6aee1867a@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> References: <20260629-msm-dp-mst-v5-0-2ed6aee1867a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782742144; l=2592; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=Mzn/mLQcqys/EJpBrtkVNH08m5/h5cbmf+/AjWnre0k=; b=6Uft3/WkZ+7eSkUNxcdPQhlD809YEyGDQXGU7xNpVLOWWKi/RrU6CCKccWgm0VLKbK47fHEWN myz3WxIbHvtAFNTJJLy8nX4oSMTB8YYJSP9KVuTn2fa4zqL/d5K6/8h X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 9Bm3pmqhSqQNF2cB0-8VeQpqju0l6agI X-Authority-Analysis: v=2.4 cv=Z4Hc2nRA c=1 sm=1 tr=0 ts=6a427e07 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=GJT6Fafo9oTAj6z5dyEA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDExOCBTYWx0ZWRfX70UnahQLdfVH uGde0w8pN08psyu3h0Lq112jp0E8/S+b8YZyHwIuP7/toOk5veCEKP6klm+qyo+Jzb35O/ktpNG XcSy7ZqjUX8oDliYn+RMGOrOvcr7cGs= X-Proofpoint-GUID: 9Bm3pmqhSqQNF2cB0-8VeQpqju0l6agI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDExOCBTYWx0ZWRfX6qHJwg1ZZ7NH j6QIf5qQbvAazmKIcr5v54eMsqqBEGtnv8DdeR6HOoW8TIdz9YMRPygIrdYiYiEWu945qG4fvAW Muqs+1dVVB88+P5qCgxnV8CpXWYY1UJ2VKM1dGqU8jB/giKuZ1i3NqfPNEwVmhbA01u81VYxXup a8CgqCXTT341UG+ZfZXGE7TfHoNSlF/RbUknoNddtc+Kcd/+ubAbppVns6PQ9a0ECDHCty8tgne yZHGBHKfk20tJyAN6VfteqeWA7M+iPJ1km1RfvGJOipIEwNIUGHU9EtCyPr72yIHuAY2V65aY8R wY9iHkKqmmNtpF5I5SRHdcXCC83BCyBYpzkCfUpqa0qTWrzbPNHWB72XpRsEVOmZJ1OVVMZDurM /Lnit65dMDXjcg++SaP+YUIuVa8Jo1REDQHFqiG7VQXqlYTWjxxbL8oSaWPqYX+q5pwsOWOOeIs M2niS/Y2QcubbHgnotQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_03,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290118 From: Abhinav Kumar Add support to program the MST enable bit in the mainlink control register when an MST session is active or being disabled. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_reg.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 6754b10d418c..e9aa0e254234 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -276,6 +276,19 @@ int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl, return 0; } +static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool enable) +{ + u32 mainlink_ctrl; + + mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + if (enable) + mainlink_ctrl |= DP_MAINLINK_CTRL_MST_EN; + else + mainlink_ctrl &= ~DP_MAINLINK_CTRL_MST_EN; + + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related interrupts */ @@ -2678,6 +2691,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); + if (ctrl->mst_active) + msm_dp_ctrl_mst_config(ctrl, true); + if (panel->stream_id == DP_STREAM_0) msm_dp_ctrl_config_ctrl_link(ctrl, panel); @@ -2731,6 +2747,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, phy = ctrl->phy; msm_dp_ctrl_mainlink_disable(ctrl); + msm_dp_ctrl_mst_config(ctrl, false); msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 6808965878d4..deb40ed24654 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -128,6 +128,10 @@ #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1) #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) +#define DP_MAINLINK_CTRL_ECF_MODE BIT(26) +#define DP_MAINLINK_CTRL_MST_ACTIVE BIT(8) +#define DP_MAINLINK_CTRL_MST_EN (DP_MAINLINK_CTRL_ECF_MODE | \ + DP_MAINLINK_CTRL_MST_ACTIVE) #define REG_DP_STATE_CTRL (0x00000004) #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) -- 2.43.0