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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF000026CA.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Mon, 29 Jun 2026 15:42:31 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 29 Jun 2026 10:41:58 -0500 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 29 Jun 2026 08:37:27 -0700 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v3 20/22] iommu/amd: Reserve translate-device-id for PCI requestor aliases Date: Mon, 29 Jun 2026 15:35:33 +0000 Message-ID: <20260629153535.15775-21-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260629153535.15775-1-suravee.suthikulpanit@amd.com> References: <20260629153535.15775-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026CA:EE_|DS0PR12MB9346:EE_ X-MS-Office365-Filtering-Correlation-Id: 0dc715b2-9734-45fd-58e4-08ded5f5083a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|82310400026|36860700016|1800799024|18002099003|22082099003|5023799004|11063799006|6133799003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QLuVbz0CpzEwlJd0bWgX1t3buwGukGsFqn0uu0Cp9qZw+1R/86iiN3DHu/Ot+oVdGdBgCCDn+KXl5DSnWANZa4kgadyUXiSmOSDV7APavk+F2Arw7WsSkmCicr7jY4xHxGG/yMYxAceM1a3WyH/xrRwOCenFOYx3M1G+91+nVv1w0s6pU2MPRp5zUGPu8Ud3lKQhsi8E69o+wqcIcE97avInJWQ5u6mCpO3ig8NONsBq8ce2gFJVtH43TQz+8LiuB61MgfsJUpdgid3sWuRx46cG/ot51jF5tHeC84tnWDFvdQbeeDorgacv3ftNuiAF99FSA2fDUHW0o8tLKaqS33OoOSQ1y57SkA3uPzandlFJ5myQFVJd0BXpIJlo3fpXoc6mTXnFILM4efGpMwI+xzI5eI/n4QgF54RG1wMXCsCppnxX02Gn8KxOuewSXGir X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2026 15:42:31.4237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0dc715b2-9734-45fd-58e4-08ded5f5083a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026CA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9346 The per-segment translate-device-id (trans_devid) pool hands out numeric device-table indices used by the AMD vIOMMU / iommufd path (e.g. mapping a KVM file descriptor to a shared trans_devid). amd_iommu_attach_device() already calls amd_iommu_trans_devid_reserve() for the struct device's own PCI BDF so that id cannot later be returned by the allocator. That is not sufficient on its own. The AMD IOMMU driver programs identical DMA translation device-table entries (DTEs) for every requestor ID that can issue DMA on behalf of the same PCI function: the IVRS alias from alias_table[] when it is not covered by the PCI DMA-alias walk (different bus than the device), and every alias visited by pci_for_each_dma_alias(). Those alternate BDFs are not separate struct device attach targets, so they never received a trans_devid reservation and could in principle collide with a dynamically allocated trans_devid. Introduce amd_iommu_trans_devid_reserve_pci_aliases() in trans_devid.c and invoke it from amd_iommu_attach_device() immediately after the primary amd_iommu_trans_devid_reserve() succeeds. For PCI devices the helper reserves the IVRS alias when it differs from the device BDF, then walks pci_for_each_dma_alias() and reserves each alias BDF. Repeated attach and overlap with the primary BDF in the PCI walk are handled by the existing idempotency of amd_iommu_trans_devid_reserve() (a second reserve of an already-reserved id succeeds). Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/iommu.c | 7 +++++ drivers/iommu/amd/trans_devid.c | 45 +++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index f99225be5d07..7300f07e7a39 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -223,6 +223,8 @@ int amd_iommu_completion_wait(struct amd_iommu *iommu); void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg); void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg); int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id); +int amd_iommu_trans_devid_reserve_pci_aliases(struct amd_iommu *iommu, + struct device *dev); #else static inline void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) { } diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 01b755a2baed..fd25c4c361f3 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3085,6 +3085,13 @@ static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev, pr_err("%s: Failed to reserve device id %#x\n", __func__, dev_data->devid); return ret; } + + ret = amd_iommu_trans_devid_reserve_pci_aliases(iommu, dev); + if (ret) { + pr_err("%s: Failed to reserve translate devid for alias of %#x (err %d)\n", + __func__, dev_data->devid, ret); + return ret; + } #endif if (dev_data->domain) diff --git a/drivers/iommu/amd/trans_devid.c b/drivers/iommu/amd/trans_devid.c index e5cca409d134..7c57087bfa10 100644 --- a/drivers/iommu/amd/trans_devid.c +++ b/drivers/iommu/amd/trans_devid.c @@ -9,6 +9,7 @@ */ #include +#include #include #include "amd_iommu.h" @@ -81,3 +82,47 @@ int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id) pci_seg->id); return ret; } + +static int reserve_trans_devid_each_dma_alias(struct pci_dev *pdev, u16 alias, + void *data) +{ + struct amd_iommu_pci_seg *pci_seg = data; + + (void)pdev; + return amd_iommu_trans_devid_reserve(pci_seg, alias); +} + +/** + * amd_iommu_trans_devid_reserve_pci_aliases - reserve translate-device-ids for + * PCI DMA aliases and for the IVRS alias when it is not walked as a PCI DMA + * alias (different bus). Idempotent for repeated attach; see + * amd_iommu_trans_devid_reserve(). + * + * Return: 0 on success or if @dev is not PCI; otherwise an errno from + * amd_iommu_trans_devid_reserve() or pci_for_each_dma_alias(). + */ +int amd_iommu_trans_devid_reserve_pci_aliases(struct amd_iommu *iommu, + struct device *dev) +{ + struct pci_dev *pdev; + struct amd_iommu_pci_seg *pci_seg; + u16 devid, ivrs_alias; + int ret; + + if (!dev_is_pci(dev)) + return 0; + + pdev = to_pci_dev(dev); + pci_seg = iommu->pci_seg; + devid = pci_dev_id(pdev); + + ivrs_alias = pci_seg->alias_table[devid]; + if (ivrs_alias != devid) { + ret = amd_iommu_trans_devid_reserve(pci_seg, ivrs_alias); + if (ret) + return ret; + } + + return pci_for_each_dma_alias(pdev, reserve_trans_devid_each_dma_alias, + pci_seg); +} -- 2.34.1