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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by BN2PEPF000055E1.mail.protection.outlook.com (10.167.245.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.202.0 via Frontend Transport; Mon, 29 Jun 2026 15:41:41 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 29 Jun 2026 10:41:35 -0500 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 29 Jun 2026 08:37:32 -0700 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v3 21/22] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Date: Mon, 29 Jun 2026 15:35:34 +0000 Message-ID: <20260629153535.15775-22-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260629153535.15775-1-suravee.suthikulpanit@amd.com> References: <20260629153535.15775-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055E1:EE_|SA5PPFAB8DFE4E8:EE_ X-MS-Office365-Filtering-Correlation-Id: fd9d6cb4-02b7-4a93-a89f-08ded5f4ea2d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|23010399003|36860700016|376014|7416014|11063799006|5023799004|56012099006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: p9JzuIWpnfkePiuknSxmeQ0j/RzkUxKYAbUWFckFvq2q4Zt0tJL3B30QgVhNhAHyYqv01bw6uywz49g2p5hzHQaq30/1Y1NWv/jIAOzUPr0kJmNKlvMSOpwbppCAiWjcWuucaTDod3LOs47YIRt26ltTWzy3LGvztyZ71lApcW8EFTrUHWGd4XoO162ATFPkJdAzEw5ZOLcRh/eyRWAibUVD+fSu2pH52WnjtIpNfkYDReWsnvj7mJJfn0NF1smu5ml0/3xddwbzPSNQBtHgOqmGUhzqbiWD2y4cCsmLUP9uPnP4k/jXCFId/qcCaeeJM/4jwM/5IMLHUt6K+BjiLDojGvVluzmRtIb/nFwKyevgNV3batKiTExXo3M9sx4StOKhnYmg+0P5UhMgsYEHg9T9WGIAqHwA22PL8W7HIvJLj8mYSzn7DFYQeffKbzMk X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2026 15:41:41.0383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd9d6cb4-02b7-4a93-a89f-08ded5f4ea2d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E1.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFAB8DFE4E8 The hardware vIOMMU uses a per-VM translate device ID (TransDevID) to index the host device table when guest IOMMU traffic needs GPA->SPA translation. The VF Control guest miscellaneous register tells the IOMMU which TransDevID to use; the corresponding device table entry (DTE) points at the nested IOMMU v1 page table that performs the walk from guest physical to system physical addresses. Add amd_iommu_set_translate_dte() and amd_iommu_clear_translate_dte() to install or clear that DTE for a given TransDevID slot through iommu_dev_data and the existing DTE update path, restoring IVRS persistent bits via amd_iommu_make_clear_dte() on teardown. Add amd_iommu_update_vfctrl_mmio_translate_devid() to publish the TransDevID in VFctrl guest-misc MMIO, and VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET for the register offset. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/iommu.c | 78 ++++++++++++++++++++++++++++- 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 91cdb61b5254..cd10e33c1317 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -495,6 +495,7 @@ extern bool amdr_ivrs_remap_support; /* VIOMMU stuff */ #define VIOMMU_VF_MMIO_ENTRY_SIZE 4096 #define VIOMMU_VFCTRL_MMIO_ENTRY_SIZE 64 +#define VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET 0x10 /* Host ioremap/request_mem_region sizes for VF / VF_CNTL BARs */ #define VIOMMU_VF_MMIO_MAP_SIZE 0x10000000UL diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index fd25c4c361f3..410c2f91064a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -213,7 +213,12 @@ void amd_iommu_update_dte(struct amd_iommu *iommu, struct dev_table_entry *new) { update_dte256(iommu, dev_data, new); - clone_aliases(iommu, dev_data->dev); + /* + * The dev_data for trans_devid does not have struct dev. + * So clone_aliases is not supported for translate-device-id. + */ + if (dev_data->dev) + clone_aliases(iommu, dev_data->dev); device_flush_dte(iommu, dev_data); amd_iommu_completion_wait(iommu); } @@ -1747,7 +1752,11 @@ static int device_flush_dte(struct amd_iommu *iommu, struct iommu_dev_data *dev_ u16 alias; int ret; - if (dev_is_pci(dev_data->dev)) + /* + * The dev_data for trans_devid does not have struct dev. + * So, it is not considered as a PCI device. + */ + if (dev_data->dev && dev_is_pci(dev_data->dev)) pdev = to_pci_dev(dev_data->dev); if (pdev) @@ -3281,6 +3290,71 @@ static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain) return true; } +#if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD) + +void amd_iommu_update_vfctrl_mmio_translate_devid(struct amd_iommu *iommu, + u16 gid, u32 devid) +{ + writeq((devid & 0xFFFFULL) << 16, + VIOMMU_VFCTRL_MMIO_BASE(iommu, gid) + + VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET); +} + +int amd_iommu_set_translate_dte(struct amd_iommu *iommu, + struct protection_domain *pdom, + u16 gid, u32 trans_devid) +{ + struct dev_table_entry new = {}; + struct iommu_dev_data *trans_dev_data; + struct pt_iommu_amdv1_hw_info pt_info; + + trans_dev_data = search_dev_data(iommu, trans_devid); + if (!trans_dev_data) { + trans_dev_data = amd_iommu_alloc_dev_data(iommu, trans_devid); + if (!trans_dev_data) { + pr_err("%s: Failed to allocate dev_data for translate-device-id %#x\n", + __func__, trans_devid); + return -ENOMEM; + } + } + + trans_dev_data->dev = NULL; + trans_dev_data->devid = trans_devid; + trans_dev_data->domain = pdom; + trans_dev_data->gid = gid; + + amd_iommu_make_clear_dte(iommu, trans_devid, &new); + /* Setup DTE for v1 page table at the offset specified by trans_devid */ + pt_iommu_amdv1_hw_info(&pdom->amdv1, &pt_info); + + pr_debug("%s: gid=%#x, iommu_devid=%#x, devid=%#x, host_pt_root=%#llx, mode=%#x\n", + __func__, gid, iommu->devid, trans_devid, pt_info.host_pt_root, pt_info.mode); + + amd_iommu_set_dte_v1(trans_dev_data, pdom, pdom->id, &pt_info, &new); + amd_iommu_update_dte(iommu, trans_dev_data, &new); + return 0; +} + +void amd_iommu_clear_translate_dte(struct amd_iommu *iommu, u32 trans_devid) +{ + struct dev_table_entry new = {}; + struct iommu_dev_data *trans_dev_data; + + pr_debug("%s: iommu_devid=%#x, trans_devid=%#x\n", + __func__, iommu->devid, trans_devid); + + trans_dev_data = search_dev_data(iommu, trans_devid); + if (!trans_dev_data) { + WARN_ON_ONCE(1); + return; + } + + amd_iommu_make_clear_dte(iommu, trans_devid, &new); + amd_iommu_update_dte(iommu, trans_dev_data, &new); + amd_iommu_free_dev_data(iommu, trans_dev_data); +} +#endif /* CONFIG_AMD_IOMMU_IOMMUFD */ + const struct iommu_ops amd_iommu_ops = { .capable = amd_iommu_capable, .hw_info = amd_iommufd_hw_info, -- 2.34.1