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[82.48.44.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47567a6f0ddsm5669083f8f.37.2026.06.30.02.26.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2026 02:27:00 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, francesco.utel@engicam.com, michael@amarulasolutions.com, domenico.acri@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v6 14/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM Date: Tue, 30 Jun 2026 11:24:43 +0200 Message-ID: <20260630092628.1695560-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260630092628.1695560-1-dario.binacchi@amarulasolutions.com> References: <20260630092628.1695560-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Support Engicam MicroGEA-STM32MP257 SoM with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM The SoM also provides an Ethernet MAC, but Ethernet support is not enabled at this stage due to a known silicon limitation documented in [1]. This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC errors"), where CRC errors may occur in ETH1 RMII direct mode when directly connected to I/Os. The workaround requires use of the Ethernet switch (ETHSW), which introduces additional DT bindings and topology complexity. This is intended to be addressed in a separate patch series. [1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Drop inclusion of stm32mp25xf.dtsi, we are using stm32mp257d. Changes in v3: - Fix a typo in the URL .../dts/st/stm32mp257-engicam-microgea.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi new file mode 100644 index 000000000000..5b4287e86def --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "Engicam MicroGEA STM32MP257 SoM"; + compatible = "engicam,microgea-stm32mp257", "st,stm32mp257"; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vddcore: regulator@b { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@e { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@10 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd3v3_usb: regulator@14 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&scmi_v3v3>; + vqmmc-supply = <&scmi_vddio2>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; -- 2.43.0