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Replace devm_clk_get_enabled() with devm_clk_get_optional() and devm_clk_prepare_enable(), and remove FSL_EDMA_DRV_HAS_CHCLK flag to simplify clock handling. Prepare to add channel runtime pm support. Reviewed-by: Frank Li Signed-off-by: Joy Zou --- Changes for v6: - Replace devm_clk_get_optional_enable() with devm_clk_get_optional() and devm_clk_prepare_enable() in order to use runtime PM for power management later. - Modify the commit message. - Add Reviewed-by tag. - Link to v5: https://lore.kernel.org/imx/20260513-b4-b4-edma-runtime-opt-v5-0-1e595bfb8423@nxp.com/ --- drivers/dma/fsl-edma-common.c | 4 +--- drivers/dma/fsl-edma-common.h | 1 - drivers/dma/fsl-edma-main.c | 22 +++++++++------------- 3 files changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index bb7531c456df..e1ca25ff228d 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -844,9 +844,7 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan) struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); int ret = 0; - if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) - clk_prepare_enable(fsl_chan->clk); - + clk_prepare_enable(fsl_chan->clk); fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ? sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd), diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 205a96489094..f4354b586746 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -210,7 +210,6 @@ struct fsl_edma_desc { #define FSL_EDMA_DRV_WRAP_IO BIT(3) #define FSL_EDMA_DRV_EDMA64 BIT(4) #define FSL_EDMA_DRV_HAS_PD BIT(5) -#define FSL_EDMA_DRV_HAS_CHCLK BIT(6) #define FSL_EDMA_DRV_HAS_CHMUX BIT(7) #define FSL_EDMA_DRV_MEM_REMOTE BIT(8) /* control and status register is in tcd address space, edma3 reg layout */ diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 36155ab1602a..1e864cd4c784 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -567,8 +567,7 @@ static struct fsl_edma_drvdata imx8qm_data = { }; static struct fsl_edma_drvdata imx8ulp_data = { - .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK | - FSL_EDMA_DRV_EDMA3, + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, .chreg_space_sz = 0x10000, .chreg_off = 0x10000, .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), @@ -808,22 +807,19 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_chan->tcd = fsl_edma->membase + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; - - if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { - snprintf(clk_name, sizeof(clk_name), "ch%02d", i); - fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, - (const char *)clk_name); - - if (IS_ERR(fsl_chan->clk)) - return PTR_ERR(fsl_chan->clk); - } + snprintf(clk_name, sizeof(clk_name), "ch%02d", i); + fsl_chan->clk = devm_clk_get_optional(&pdev->dev, (const char *)clk_name); + if (IS_ERR(fsl_chan->clk)) + return PTR_ERR(fsl_chan->clk); + ret = devm_clk_prepare_enable(&pdev->dev, fsl_chan->clk); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to enable clock\n"); fsl_chan->pdev = pdev; vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); fsl_edma_chan_mux(fsl_chan, 0, false); - if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) - clk_disable_unprepare(fsl_chan->clk); + clk_disable_unprepare(fsl_chan->clk); } ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); -- 2.34.1