From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 906F53F4DFD for ; Wed, 1 Jul 2026 08:48:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895734; cv=none; b=tZi59l/ZcJgJabLxVn9gTAbwaWDvJ7wndrpb+f/79o39onQpif/+OdhXaFoMlzVe0CXD8OXpM7kzoxHi03vA31AcaXqWYN1qyx5xjtE6FteYPCOp+yPIOQHjTIFRXN/dt2ePxXhoEmojKp1kXkpmwk/Q6Kb528Y2aGHZnHw9fPA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895734; c=relaxed/simple; bh=hHbdnttRcIwSaLlig0mRieB9Ne9ycoY/WHmdXhNxYJQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DD8qWzdbGu+FBNvbovReLUHxvWz5FOmaAnpvVYR0RBqtwai20yhP61HIphwSCGO3Q6k+2HAP61Ur03Z4YlwoSQty9Mb/ofFRJtai0L17CK1RjsSRe8CcyyCRL09o9mq9Z/dQaJJrfGNDjbYwEIxKwcDr+XNn3396irZ2p1GJWmw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Fj1VyxK7; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Fj1VyxK7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895730; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B7OAVI61QCG9swWmfE7yqtDuGV/OQ+fEPL58DyfrzLw=; b=Fj1VyxK7J+37FD7vP9f/P93B/DY/Pvc34Fgtk6N2PFXTDVG8akv8TcGw1hsFJliVwrOlOb BSU4fGnAhfS+S5d924d78fX6gm0L0wYsAEgtcyeFkL/iLogIpWJMuHj6pOdDrJ4jOJqopc kNdSXuYhvcjSKckGAt5v6EEwM3bnBgo= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:06 -0700 Subject: [PATCH v8 18/22] RISC-V: perf: Add Qemu virt machine events Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260701-counter_delegation-v8-18-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Qemu virt machine supports a very minimal set of legacy perf events. Add them to the vendor table so that users can use them when counter delegation is enabled. Qemu is identified by its marchid. Older Qemu reports all-zero mvendorid/marchid/mimpid, while newer Qemu reports the marchid 0x2a (42) allocated to it in the RISC-V ISA manual [1]. Register the events for both ids so they are available across Qemu versions. [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md Signed-off-by: Atish Patra --- arch/riscv/include/asm/vendorid_list.h | 6 ++++++ drivers/perf/riscv_pmu_sbi.c | 39 ++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index 7f5030ee1fcf..beaf9236dba7 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -11,4 +11,10 @@ #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#define QEMU_VIRT_VENDOR_ID 0x000 +#define QEMU_VIRT_IMPL_ID 0x000 +#define QEMU_VIRT_ARCH_ID 0x000 +/* Newer Qemu reports the spec-allocated marchid 0x2a (42) for non-vendor CPUs */ +#define QEMU_VIRT_ARCH_ID_SPEC 0x2a + #endif diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8d56bef95a1b..6d528eafb525 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -469,7 +470,45 @@ struct riscv_vendor_pmu_events { .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \ .attrs_events = _attrs }, +/* QEMU virt PMU events */ +static const struct riscv_pmu_event qemu_virt_hw_event_map[PERF_COUNT_HW_MAX] = { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] = {0x01, 0xFFFFFFF8}, + [PERF_COUNT_HW_INSTRUCTIONS] = {0x02, 0xFFFFFFF8} +}; + +static const struct riscv_pmu_event qemu_virt_cache_event_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + PERF_CACHE_MAP_ALL_UNSUPPORTED, + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10019, 0xFFFFFFF8}, + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = {0x1001B, 0xFFFFFFF8}, + + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10021, 0xFFFFFFF8}, +}; + +RVPMU_EVENT_CMASK_ATTR(cycles, cycles, 0x01, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFFF8); + +static struct attribute *qemu_virt_event_group[] = { + RVPMU_EVENT_ATTR_PTR(cycles), + RVPMU_EVENT_ATTR_PTR(instructions), + RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), + RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + NULL, +}; + static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID, QEMU_VIRT_IMPL_ID, + qemu_virt_hw_event_map, qemu_virt_cache_event_map, + qemu_virt_event_group) + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID_SPEC, QEMU_VIRT_IMPL_ID, + qemu_virt_hw_event_map, qemu_virt_cache_event_map, + qemu_virt_event_group) }; static const struct riscv_pmu_event *current_pmu_hw_event_map; -- 2.53.0-Meta