From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-173.mta0.migadu.com (out-173.mta0.migadu.com [91.218.175.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96FBF3F0779 for ; Wed, 1 Jul 2026 08:49:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.173 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895745; cv=none; b=ufsfOuhZjUxR+iyaDWY7Suf0/JWu0D680bSEGRTHq1bC1ogT46z/YAKyP/Rg6vDVgKQmBTzfUAenZArlGVN15m2AKA8v+5ytaQxtZ2GPNfGtwQZk9ojtvmi/V9lP/gGvY59fFt2DjnZaFr7Aj0oQ/yhV5NERw0SIkoihKmM+l78= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895745; c=relaxed/simple; bh=TRQUQK1N1laVmfi+/z8Tzbr63EM/xjtFPowISmSkmco=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Swd8ZWHIIVsryzNVGxUnlKnhB+4PHAeuvXwGL8wF7532lqSWZ0muIa8bywNouiQoJksHuGK2W5QYdbisEUGAOPTNCl78BjpkuTvpuepTHQUO1xTaw2alcf+I/ymkvbuDrKOpCpTBlJObEEoyg6HVnqmJdJypn54bxK8y11uNAb4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=uiLH+Uh9; arc=none smtp.client-ip=91.218.175.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="uiLH+Uh9" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S8V8xtoKAqPlqqdP66L19gg4AeWHREfPI94nLKFh6Tk=; b=uiLH+Uh9dSNQoPC8h35NhiprnhamkymjKrSZfhp5i7VWRDdYEQfxzf1+izxnVLZHjMPFdW Irb4Biq7+mvnafDeeOOeK+cLN8zFyvXbp+2h/MBYrmuZn6bRvcgDio4rKEq1dCP5yqytrR boC+/qSkoW2lzlnlYwySyWjT3Gviwc8= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:09 -0700 Subject: [PATCH v8 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260701-counter_delegation-v8-21-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Adds fake-any/fake-ctr3/fake-ctr34 (event codes 0xF0x QEMU doesn't model) with counterid_masks, to exercise the counter-delegation allocation + counter-mask constraint in QEMU (events read 0 = allocated/programmed, vs 'not supported'). Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 6d528eafb525..725816c274e5 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -492,6 +492,12 @@ RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFFF8); RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFFFFF8); RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFFF8); +/* + * FAKE events for cdeleg mechanism testing: event codes QEMU does NOT model. + */ +RVPMU_EVENT_CMASK_ATTR(fake-any, fake_any, 0xF00, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(fake-ctr3, fake_ctr3, 0xF01, 0x8); +RVPMU_EVENT_CMASK_ATTR(fake-ctr34, fake_ctr34, 0xF02, 0x18); static struct attribute *qemu_virt_event_group[] = { RVPMU_EVENT_ATTR_PTR(cycles), @@ -499,6 +505,9 @@ static struct attribute *qemu_virt_event_group[] = { RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(fake_any), + RVPMU_EVENT_ATTR_PTR(fake_ctr3), + RVPMU_EVENT_ATTR_PTR(fake_ctr34), NULL, }; -- 2.53.0-Meta