From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A41F340A6B; Wed, 1 Jul 2026 03:54:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782878099; cv=none; b=LYIFyWrglYQR/Xet+6MfISxfjozSdhk1tXRA7AGbxYl7bb3kwmakPqNVdh4GjIc/p86bDgs0WdHb5ZvOqyWaE5o6LznDUXZPFesMi9oIadljdI6cx5BYBL5kOODnrPaMSCU1/qudJZ0r/HE86VMl2bzIpyXwd7eAJBOpIx7XKp4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782878099; c=relaxed/simple; bh=Yd4SDkZd6V+uRHny0US4o+Yy2cEk8Dx7jFc3u2LOzrI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EfrMy2l6PgJ1D9g8gl6dJJD+9cSrhEjDLm6FS02ZwLR7NqSx1Qx89710U84L/R/mMMGnIzB/Gn3j5Om/Bnduv1Q72tzvgMJYFN2TLFDa4Pe/dqwJk0XJt9gdOgQNfTDK/bnJ/ZsJY4qZ/0QSuzDAUTFuj9BgfASVx06ALAuNc6M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.177]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4gqmN02JzQzYQtrh; Wed, 1 Jul 2026 11:53:52 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.252]) by mail.maildlp.com (Postfix) with ESMTP id 2DAF24058F; Wed, 1 Jul 2026 11:54:46 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP3 (Coremail) with UTF8SMTPA id _Ch0CgBXiyWAj0RqCne9AQ--.26189S15; Wed, 01 Jul 2026 11:54:45 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Li Huafei Cc: Peter Zijlstra , leo.yan@linux.dev, Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v3 13/21] perf annotate-arm64: Enable instruction tracking support Date: Wed, 1 Jul 2026 03:53:47 +0000 Message-Id: <20260701035355.752944-14-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260701035355.752944-1-wutengda@huaweicloud.com> References: <20260701035355.752944-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:_Ch0CgBXiyWAj0RqCne9AQ--.26189S15 X-Coremail-Antispam: 1UD129KBjvJXoWxCry5tF48tryxZr18ZFWkWFg_yoWrCry7pa yDC345Gry5Jr4IgwnxZrs7Xry3Cw4xW34Y9r1Yg392yFnFyr95tFs3KFWakF4rJrZ3Cw47 t3WqyF4UX3y7CaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHYb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAV Cq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0 rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY1x0267 AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E 14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7 xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Y z7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6x kF7I0E8cxan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r 18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAI cVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0piPkusUUUUU= X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Enable basic instruction tracking for arm64 by implementing three essential functions in the find_data_type_block() call path: find_data_type_block -> arch_supports_insn_tracking (1) -> find_data_type_insn -> init_type_state (2) -> update_insn_state (3) Changes: * arch_supports_insn_tracking(): add arm64 to the list of supported architectures, allowing find_data_type_block() to proceed with data type analysis. * init_type_state(): correctly identify ret_reg, stack_reg, and caller-saved registers for arm64 during type state initialization. * update_insn_state(): add the update_insn_state_arm64() callback with no instruction support yet. More instructions will be enabled gradually in later patches. With these changes, arm64 gains support for basic variable type inference during instruction tracking. Signed-off-by: Li Huafei Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 30 +++++++++++++++++++ tools/perf/util/annotate-data.c | 11 ++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/util/annotate-arch/annotate-arm64.c index 77b6f4841c84..48b1c94273eb 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -9,6 +9,8 @@ #include #include "../annotate.h" #include "../disasm.h" +#include "../annotate-data.h" +#include "../debug.h" struct arch_arm64 { struct arch arch; @@ -324,6 +326,31 @@ static int extract_op_location_arm64(const struct arch *arch, return 0; } +#ifdef HAVE_LIBDW_SUPPORT +static void update_insn_state_arm64(struct type_state *state, + struct data_loc_info *dloc, Dwarf_Die *cu_die __maybe_unused, + struct disasm_line *dl) +{ + struct annotated_insn_loc loc; + struct annotated_op_loc *dst = &loc.ops[INSN_OP_TARGET]; + u32 insn_offset = dl->al.offset; + + if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) + return; + + /* + * For unsupported instructions with a destination register, invalidate + * the destination register itself to prevent incorrect type propagation. + */ + if (has_reg_type(state, dst->reg1)) { + pr_debug_dtp("%s [%x] invalidate reg%d\n", + dl->ins.name, insn_offset, dst->reg1); + invalidate_reg_state(&state->regs[dst->reg1]); + return; + } +} +#endif + const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, const char *cpuid __maybe_unused) { @@ -343,6 +370,9 @@ const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id, arch->objdump.imm_char = '#'; arch->associate_instruction_ops = arm64__associate_instruction_ops; arch->extract_op_location = extract_op_location_arm64; +#ifdef HAVE_LIBDW_SUPPORT + arch->update_insn_state = update_insn_state_arm64; +#endif /* bl, blr */ err = regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-data.c index 104b80d471f1..c51b20a7af9b 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -28,6 +28,7 @@ /* register number of the stack pointer */ #define X86_REG_SP 7 +#define ARM64_REG_SP 31 static void delete_var_types(struct die_var_type *var_types); @@ -178,6 +179,13 @@ static void init_type_state(struct type_state *state, const struct arch *arch) state->regs[11].caller_saved = true; state->ret_reg = 0; state->stack_reg = X86_REG_SP; + } else if (arch__is_arm64(arch)) { + int i; + + for (i = 0; i < 18; i++) + state->regs[i].caller_saved = true; + state->ret_reg = 0; + state->stack_reg = ARM64_REG_SP; } } @@ -1437,7 +1445,8 @@ static enum type_match_result find_data_type_insn(struct data_loc_info *dloc, static int arch_supports_insn_tracking(struct data_loc_info *dloc) { - if ((arch__is_x86(dloc->arch)) || (arch__is_powerpc(dloc->arch))) + if (arch__is_x86(dloc->arch) || arch__is_powerpc(dloc->arch) || + arch__is_arm64(dloc->arch)) return 1; return 0; } -- 2.34.1