From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 927973B27EE for ; Wed, 1 Jul 2026 09:42:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782898945; cv=none; b=YqCmSIch/gtUE3PSpcW7pY+R0vlIW72VmoE85Xyu/yF03AyV5jlFtjJYsQGZXpIsRO5MYE/GMjOkZ50uGmWFUTddm7Y2KP8aNHGLy4SqpVnvJPbeEF8dsgPcEtQuxSCGLSvoZTr9F+GDm42s9JK2zxwxHJagy4GqZ6VbIEztHFo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782898945; c=relaxed/simple; bh=uWS/sPdkOJugaAxTUZRNeodfhNhiiCyeDP95Fb2/glk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k2R/FoZgWE8S/38bn/P9RJE+gHZdXBULUzmWF8AYXjDBZTEnjFyGsY6wxpuq7xR6X9L6h3xqTl0CKOaf2KMZliQpfaMlthshJaQUGxs0iCFPJQZaXJwF6143rKj4fCWqKXfk+pGclxea6lfS9cGqkYPv7EEpFAK2tEoIJ1/wiiQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=WJXANi1I; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="WJXANi1I" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56E5B22FC; Wed, 1 Jul 2026 02:42:18 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5FA513F905; Wed, 1 Jul 2026 02:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1782898942; bh=uWS/sPdkOJugaAxTUZRNeodfhNhiiCyeDP95Fb2/glk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WJXANi1Ify3x1Brx48MOayidx2YzNfQxgqTThkmw/Q/vfy1PegYNrP7opSiSUqw6Y CRJcnZTBXWGxjf8mEEojdGLHFvRbgv8qb7jTONOWO6/8Kv5WEfv0v3Br+U21RGQnXS ZSCurtpAiL7j0SZ6mnnvEc5v4+Bl7IvfpgR+ye+0= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH 3/5] arm64: cputype: Add Cortex-A520AE definitions Date: Wed, 1 Jul 2026 15:11:29 +0530 Message-ID: <20260701094131.677636-4-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260701094131.677636-1-linu.cherian@arm.com> References: <20260701094131.677636-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add cputype definitions for Cortex-A520AE. The definition can be found in Cortex-A520AE TRM, https://developer.arm.com/documentation/107726/0001/ as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Signed-off-by: Linu Cherian --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 1b9f0cda1336..e41fae46426b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -82,6 +82,7 @@ #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A520 0xD80 +#define ARM_CPU_PART_CORTEX_A520AE 0xD88 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 @@ -176,6 +177,7 @@ #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) +#define MIDR_CORTEX_A520AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520AE) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) -- 2.43.0