From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5208B3F787E for ; Wed, 1 Jul 2026 09:42:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782898948; cv=none; b=WVHlhVYp2MyDiLcBYY7cchxGemDJ3EAZGFah9pzidVRVChSrg+t5rWexQSb6d5TiSq2pqzvYAx/740ZCcWM3vbQIYfRd1+n7fUb4jc2RA3K9hBHn6f5qftOymIkQ4Wcg/PU1kbrEAdjT2VUCGl+EvuDPnc970jNwP+UdDsBCHvI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782898948; c=relaxed/simple; bh=da+1swfZL2auAVAa38gH0HjBTNkoIG9H/N2feo5/2Pc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RYiqp4SrwZUApz8lbNN57Qnd2TXAk/EVKTwKSrHMDtKPE6an3SgCIutu5fug5YD4YQdawVoF6hQTy39x+mRlFJy+LGYJpecxC7LPgFlzuxnyYwj52pvVBpWKlf8Vr0iykfjM0WeFQi9T6Hrs/ehwRtdY3vy87R5QC5juPG6GA9g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=nYsVdN0w; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="nYsVdN0w" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5232522FC; Wed, 1 Jul 2026 02:42:22 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5ABE03F905; Wed, 1 Jul 2026 02:42:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1782898946; bh=da+1swfZL2auAVAa38gH0HjBTNkoIG9H/N2feo5/2Pc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nYsVdN0w0L7jSakW+RvnaaYVIOv072pjcwpsn8ASAurQ/4JZH3aYGicFSdjPEOhkV waOmXPzBExSLQEXhLIU519X3lPl40e6F3VZVkYw4YJzDHQyhyA21HucT5QcKJuhWGZ LQeWoW9NFvr0cmdEqk9mSb7YSDUFKHdjgvQTStAs= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH 4/5] arm64: cputype: Add C1-Nano definitions Date: Wed, 1 Jul 2026 15:11:30 +0530 Message-ID: <20260701094131.677636-5-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260701094131.677636-1-linu.cherian@arm.com> References: <20260701094131.677636-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add cputype definitions for C1-Nano. The definition can be found in C1-Nano TRM, https://developer.arm.com/documentation/107753/0002 as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Signed-off-by: Linu Cherian --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index e41fae46426b..1fa29616e586 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -100,6 +100,7 @@ #define ARM_CPU_PART_CORTEX_A720AE 0xD89 #define ARM_CPU_PART_C1_ULTRA 0xD8C #define ARM_CPU_PART_NEOVERSE_N3 0xD8E +#define ARM_CPU_PART_C1_NANO 0xD8A #define ARM_CPU_PART_C1_PRO 0xD8B #define ARM_CPU_PART_C1_PREMIUM 0xD90 @@ -195,6 +196,7 @@ #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO) #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) -- 2.43.0