From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f202.google.com (mail-oi1-f202.google.com [209.85.167.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A8563B8BC6 for ; Wed, 1 Jul 2026 20:43:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.202 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782938631; cv=none; b=nqDCxkb68Q0khM8KxlKwpM1g8nSZAZqxq4gYMgwEckl4/AteNhqhFd4mammIjeOQ40GN3c2U4UdYgh5Hc542kXn3vRgQ5hZ4EYC81BkE6s55wfuUreS7HAeHF7ZmusOq1fPyf/FCI6AnEXrTr9U/bksYgT2KNek8NdggzfQMw/Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782938631; c=relaxed/simple; bh=o3KE/c4h20q430m4u503sTesvQ9Ro+QbUhfL64h7kLk=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=hORHgVVzEjeso86+EJt1Gm4gXaHer8NT2RVnCQeXIyWzUBtgZnRZbNCjJAp/MdMsfbTH+kTKw3iUKvIAEl9X2CDD3ubYdVktrvBLRLd5WXl7rQPG9djETN+rTwzMd4Jv7yeUKkOFmRjr2HpwKhImxSv03M1qU1cJZZUUHqE2cUs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=YtUAvwDy; arc=none smtp.client-ip=209.85.167.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="YtUAvwDy" Received: by mail-oi1-f202.google.com with SMTP id 5614622812f47-495f946aaffso2306219b6e.1 for ; Wed, 01 Jul 2026 13:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1782938627; x=1783543427; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=tFUa7znH4M21s1U2YoShafNp4F1ZnEDYd6H2bCRg/JI=; b=YtUAvwDygnwUjnCahnTZwgVOhmNqmNyJZZ0De61jFrGBsGMkw7rZlmGArEP0fWZBKd WZqZRHM4eXlV+9lCOd8qI8RuyUtvkITwIb6x6grCEf3SlxkCUW9q9PU9PVRmucBn6/d+ Eq/iC5lah4NzzdPsF1Aha7Pis1w8SCgJw5X8PS1rHHW7fuFaP0gxJL3ThoQNXowboVJ/ KPPhftnJi4b5ojZSFFEkLMDsMdFgAfOmNgq1sU/11WS9mR0MmIUUHuzEsAi3IGJqzwUN dlXmQEppeyu4OTV4hWBBQ7lo/mEsaqPRT7RkxPJmr0CTMs7Kl/ipLf8NJKgYanYcafTh xa7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782938627; x=1783543427; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=tFUa7znH4M21s1U2YoShafNp4F1ZnEDYd6H2bCRg/JI=; b=qugcv0g3vbG441y2iPEP0/wWtm9M9IWgFNRfWg2fF7sf+iA4jTmIOBW4sOTZLt/ymd WtuQ1ePzeve+fSBoIQOs7zIbeQtEpm4XFWRhuhdw88Ar7qWOHa1+6RTaFHkAhP9EO2rh mr1tSSKdWlqNhQ2sp58JiKF7wijUJlVD0qwX85wwTIPkxww/VaxZgJcuvYMIGOPI63us LckGEiLNFXKecwzymUD+1ChdwsOhf8m3NuFObtiLOviAQuOU9D4b2dcZYPEjc4KUZ1Yc GS27AGUNbg7ZjWY1+SSx3aen8QgwRqYLrrFZA358VTSyhA+3+O8RJ1vUpfaD9FFeM4/8 Lytw== X-Forwarded-Encrypted: i=1; AFNElJ/aKU7NVYw0VENw15fG7jYhIyuHswIFtr6LerYAHo/fvl3FT/WDzddI6q0ixYlCunRVahncWKEWe1LzjGc=@vger.kernel.org X-Gm-Message-State: AOJu0YxivZ6A2xuFSPC47x4/iZ0Z6UFHMMhquEygICJYb5In2bHI5lbU LehjL0GcrhgljorlSjDfTbHfwiQdzu8Lo91F7Ks6PrITY/XEWGheoTn8CkiISxgI/BhwsJvljo4 WVY0KWhd5v4ZQfLk2pyYJy5r4iQ== X-Received: from ilb3-n1.prod.google.com ([2002:a05:6e02:5303:10b0:503:bd20:d827]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:c3ee:b0:495:ca1b:7865 with SMTP id 5614622812f47-495f502375fmr5855417b6e.11.1782938626972; Wed, 01 Jul 2026 13:43:46 -0700 (PDT) Date: Wed, 1 Jul 2026 20:43:41 +0000 In-Reply-To: <20260701204342.2654385-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260701204342.2654385-1-coltonlewis@google.com> X-Mailer: git-send-email 2.55.0.rc2.803.g1fd1e6609c-goog Message-ID: <20260701204342.2654385-5-coltonlewis@google.com> Subject: [PATCH 4/5] KVM: arm64: Initialize HCR_EL2.E2H early From: Colton Lewis To: stable@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Mark Rutland , Ahmed Genidi , Ben Horgan , Leo Yan Content-Type: text/plain; charset="UTF-8" From: Mark Rutland [ Upstream commit 7a68b55ff39b0d2dcd92ee241b12b23a7e03c621 ] On CPUs without FEAT_E2H0, HCR_EL2.E2H is RES1, but may reset to an UNKNOWN value out of reset and consequently may not read as 1 unless it has been explicitly initialized. We handled this for the head.S boot code in commits: 3944382fa6f22b54 ("arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative") b3320142f3db9b3f ("arm64: Fix early handling of FEAT_E2H0 not being implemented") Unfortunately, we forgot to apply a similar fix to the KVM PSCI entry points used when relaying CPU_ON, CPU_SUSPEND, and SYSTEM SUSPEND. When KVM is entered via these entry points, the value of HCR_EL2.E2H may be consumed before it has been initialized (e.g. by the 'init_el2_state' macro). Initialize HCR_EL2.E2H early in these paths such that it can be consumed reliably. The existing code in head.S is factored out into a new 'init_el2_hcr' macro, and this is used in the __kvm_hyp_init_cpu() function common to all the relevant PSCI entry points. For clarity, I've tweaked the assembly used to check whether ID_AA64MMFR4_EL1.E2H0 is negative. The bitfield is extracted as a signed value, and this is checked with a signed-greater-or-equal (GE) comparison. As the hyp code will reconfigure HCR_EL2 later in ___kvm_hyp_init(), all bits other than E2H are initialized to zero in __kvm_hyp_init_cpu(). Fixes: 3944382fa6f22b54 ("arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative") Fixes: b3320142f3db9b3f ("arm64: Fix early handling of FEAT_E2H0 not being implemented") Signed-off-by: Mark Rutland Cc: Ahmed Genidi Cc: Ben Horgan Cc: Catalin Marinas Cc: Leo Yan Cc: Marc Zyngier Cc: Oliver Upton Cc: Will Deacon Link: https://lore.kernel.org/r/20250227180526.1204723-2-mark.rutland@arm.com [maz: fixed LT->GE thinko] Signed-off-by: Marc Zyngier [ Backport: Resolved conflict in arch/arm64/kvm/hyp/nvhe/hyp-init.S by extracting EL2 state initialization into __kvm_init_el2_state and calling it after HCR setup. ] --- arch/arm64/include/asm/el2_setup.h | 26 ++++++++++++++++++++++++++ arch/arm64/kernel/head.S | 19 +------------------ arch/arm64/kvm/hyp/nvhe/hyp-init.S | 16 +++++++++++++--- 3 files changed, 40 insertions(+), 21 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index b7afaa026842b..3498dc5d02c18 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -16,6 +16,32 @@ #include #include +.macro init_el2_hcr val + mov_q x0, \val + + /* + * Compliant CPUs advertise their VHE-onlyness with + * ID_AA64MMFR4_EL1.E2H0 < 0. On such CPUs HCR_EL2.E2H is RES1, but it + * can reset into an UNKNOWN state and might not read as 1 until it has + * been initialized explicitly. + * + * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but + * don't advertise it (they predate this relaxation). + * + * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H + * indicating whether the CPU is running in E2H mode. + */ + mrs_s x1, SYS_ID_AA64MMFR4_EL1 + sbfx x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH + cmp x1, #0 + b.ge .LnVHE_\@ + + orr x0, x0, #HCR_E2H +.LnVHE_\@: + msr hcr_el2, x0 + isb +.endm + .macro __init_el2_sctlr mov_q x0, INIT_SCTLR_EL2_MMU_OFF msr sctlr_el2, x0 diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index e0e710b36da37..ff7769821166a 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -575,25 +575,8 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) msr sctlr_el2, x0 isb 0: - mov_q x0, HCR_HOST_NVHE_FLAGS - - /* - * Compliant CPUs advertise their VHE-onlyness with - * ID_AA64MMFR4_EL1.E2H0 < 0. HCR_EL2.E2H can be - * RES1 in that case. Publish the E2H bit early so that - * it can be picked up by the init_el2_state macro. - * - * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but - * don't advertise it (they predate this relaxation). - */ - mrs_s x1, SYS_ID_AA64MMFR4_EL1 - tbz x1, #(ID_AA64MMFR4_EL1_E2H0_SHIFT + ID_AA64MMFR4_EL1_E2H0_WIDTH - 1), 1f - - orr x0, x0, #HCR_E2H -1: - msr hcr_el2, x0 - isb + init_el2_hcr HCR_HOST_NVHE_FLAGS init_el2_state /* Hypervisor stub */ diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/hyp-init.S index 1cc06e6797bda..a08363b9b10fd 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S @@ -75,6 +75,16 @@ __do_hyp_init: eret SYM_CODE_END(__kvm_hyp_init) +/* + * Initialize EL2 CPU state to sane values. + * + * HCR_EL2.E2H must have been initialized already. + */ +SYM_CODE_START_LOCAL(__kvm_init_el2_state) + init_el2_state // Clobbers x0..x2 + finalise_el2_state + ret +SYM_CODE_END(__kvm_init_el2_state) /* * Initialize the hypervisor in EL2. * @@ -202,9 +212,9 @@ SYM_CODE_START_LOCAL(__kvm_hyp_init_cpu) 2: msr SPsel, #1 // We want to use SP_EL{1,2} - /* Initialize EL2 CPU state to sane values. */ - init_el2_state // Clobbers x0..x2 - finalise_el2_state + init_el2_hcr 0 + + bl __kvm_init_el2_state __init_el2_nvhe_prepare_eret /* Enable MMU, set vectors and stack. */ -- 2.55.0.rc2.803.g1fd1e6609c-goog