From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BA98370D5A for ; Thu, 2 Jul 2026 19:14:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783019700; cv=none; b=Fg8sAwj4pswBlhHpMz57D0L5VzZ5gmX9nBgM1Avoo6weeR16T01dMLINbhOpMOrgVj6Ej6f0PiCI0KjnsPJLMPOMEAaHHA+/OxgNqF78CVvoSmH2xo4IWdIVi3QStUtkwHUBBWUbT3QdoR+cXcHtCA7E7KPRpmZeYipVxzEHPTo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783019700; c=relaxed/simple; bh=xM6NQHWl+Dt8zD7RchVRavjCeaB+a+Le6syKuTiV13w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=PwnqQ1YMvTplvZl+2oDDwKrwZHMMglXbC8PtSi4Crx0p46OQsoZXxwBM+pQ8CxOAZLtvluMjRdd8cf7aCUH+Dulc/ODM7OCzRBn3b4OYAdwHWiO8t7rSXoZFjrn9i1WvLzwjI6jOiCO5QYc9qy3lICe9zir3duozuf5w0w2kPdg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KrjLEjSP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KrjLEjSP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ABF691F000E9; Thu, 2 Jul 2026 19:14:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783019698; bh=SH7WQ9SiDmPMZjRW1eSq8yZFjs2MRMTIkpOwzk9G5V4=; h=From:Date:Subject:To:Cc; b=KrjLEjSP4FiHTUsd/cegqj0k8a4XS8Yg2wuGlC5ffjrDDiqfnd9D9A9ALDizhzSsZ m+c6QAICxeCGvAs3WVN75eRmDvYb0uUuo8QYddDppQ4dSHW1nIhj1CLm5FRiAjEvhu 4J6sqCL+329qgryhhQgGBfDF+hb+644Gt5e5uWi0pdoFicG2bUFxjKmIo3fqBu+20r sHr5EqcNkzISd8XwzPAlzGe1gaF+leFXjbeEXKDZBNtPwzGJBpFd7FZfsghcgITVbw hqVNRIJvYB+U/fiJvkag6A6LOYuPDhf97ZLO3aE7voThAm1Jz3sVG2V5kSM7fMQbnr Mob0IhMmhIgdQ== From: Mark Brown Date: Thu, 02 Jul 2026 20:13:35 +0100 Subject: [PATCH] arm64: mm: When logging data aborts only decode Xs when ISV=1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260702-arm64-xs-decode-v1-1-64600f149969@kernel.org> X-B4-Tracking: v=1; b=H4sIAF64RmoC/yXMTQqDMBBA4avIrDuQsTGIV5Eu0mTUEfwho0UQ7 97YLr/FeycoJ2GFpjgh8UdUljmDHgWEwc89o8RsKE3pjKMafZqcxUMxclgio/f0JGfJ2KqCXK2 JOzl+x/b1t+7vkcN2b+C6vkN/yUhzAAAA X-Change-ID: 20260618-arm64-xs-decode-aa1316410455 To: Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1954; i=broonie@kernel.org; h=from:subject:message-id; bh=xM6NQHWl+Dt8zD7RchVRavjCeaB+a+Le6syKuTiV13w=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqRriwhS37La+L4a041/nb4xr0U19aTrdaxha/z Yp5Nz3JqQyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaka4sAAKCRAk1otyXVSH 0LkMB/wKOqD20NDH9z5OeLLuvsdOzYcGjOehHr4Byr7RBXfkCsumnuhLwWbd6BeJBEwOWyNIEHO /usVB0nmD0+5GxQQilX9PPE3j7PG0ia+Nj7FcZtAR6DXlho1fv+ZBh1RN3uW7ST6z9uB1ifVO8l 5qofqCEzXNbFJeFr4SFGeIhAh4UGTDN6afoycFFrqF9PrxsmX1aJgKGK38lWn+ObhtQiS4ZfdX/ rqBHfa3NzPGGrBeXXLzJzTHEhpG1Uu34GhH+dYLkFHKGD3KBzPh2HWKCJWG6L1K9cWN2Aq79TjD Cby/M1jyjJQN7JhvkFDkPet8XSLwAaNN5Mo7Wji7dxVTwH2h X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When logging the decode of a data abort we currently unconditionally decode and display Xs. Currently the only defined non-RES0 values for this field are for cases where ISV=1, move the decode of Xs into our existing check for ISV=1. This avoids potential confusion if some other use is assigned to these bits for ISV=0 cases in future, or misleading someone into thinking there is a meaningful value there with currently defined architecture. Signed-off-by: Mark Brown --- arch/arm64/mm/fault.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 85e23388f9bb..0b52557652be 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -76,6 +76,8 @@ static void data_abort_decode(unsigned long esr) pr_alert(" SF = %lu, AR = %lu\n", (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); + pr_alert(" Xs = %llu\n", + (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT); } else { pr_alert(" ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n", esr & ESR_ELx_ISS_MASK, iss2); @@ -87,11 +89,10 @@ static void data_abort_decode(unsigned long esr) (iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT, (iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT); - pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu, Xs = %llu\n", + pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu\n", (iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT, (iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT, - (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT, - (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT); + (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT); } static void mem_abort_decode(unsigned long esr) --- base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482 change-id: 20260618-arm64-xs-decode-aa1316410455 Best regards, -- Mark Brown