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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5aec8991affsm626240e87.13.2026.07.02.04.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 04:40:29 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 02 Jul 2026 14:40:26 +0300 Subject: [PATCH 2/2] phy: qcom-qusb2: fix autoresume handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260702-fix-qusb2-v1-2-b5cf55621524@oss.qualcomm.com> References: <20260702-fix-qusb2-v1-0-b5cf55621524@oss.qualcomm.com> In-Reply-To: <20260702-fix-qusb2-v1-0-b5cf55621524@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Kathiravan T , Baruch Siach , Dmitry Baryshkov , Krishna Kurapati Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5398; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=mZMDOZsidMvP4Sf7A/yARzoaVsw7RzwuGmMvlmFgEYU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqRk4phLT9hZHptz2O7KfLs3K9OZFhzyFpChdtF KYg0OYYms2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCakZOKQAKCRCLPIo+Aiko 1Q6/CACPuzxmqJ8UhIx9wTczhBRB6KVAqPOWFo1rWA5GjmYW7pDcCDuZhNC38MIJODmpfv6JQwc PkfFi2f4NX73BeWYfoDu9wMHqHtKaNmA9M2VDYeA14HIqY4spEk/tdL6z6M6FE+1fPtIT0HlmY2 Bir8p3rB22cZWKyxa661hl0tXO+v5/29ObXngPsxr2AgGCGg3Dj4z8eUzZReDwiMafJI+tFbX1O ElwbXFn8rjH34xKOYYAUbOgEGs+OU4eqP4DaGennA9J8fJgSqhAdhad1DBVKfnDnEBZCwvdy8FY DrvVMYecwApMUzVoSL7F33fJtMo9bKSvNx6LbwYx+7I5h0Ao X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: dkyrCpkb3k-wBFV9hFYxXzTtbQx2CSpe X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAyMDEyMSBTYWx0ZWRfX5EZ9R1495b7J OuGUmHXRSpaYR6FDKLx3eJqHEkk/1OqMsXSQn7kBirY02h9ZBydTFkH2gmkzk8rOqjAJPJYKTmz mCap/iocg+n2/WyD2T++pwMOk5aGZjU= X-Authority-Analysis: v=2.4 cv=aJ7Ab79m c=1 sm=1 tr=0 ts=6a464e30 cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=6YfJv8JmAF87wY5fNyEA:9 a=QEXdDO2ut3YA:10 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAyMDEyMSBTYWx0ZWRfX5iwHBw0iY7C5 +MK6XLvFRjTLfW1m38HNtqRdnJmsiPo9801OTPif4JXrDfIKmXZoSDVYn8eSZZfNw5qy0afX2P4 wZudsarw/yZ8eiIjr5FW001MEqq+eqOjfw5vWoMrjez++eR/jYM/ibDzrry7IijPgVBmzTG6cvF 3kkEB+/ZCHX75zpuvEqY6qC1VZxUne9Jnzw7zqjoj8I4jla186y+pQemc7/nspBBL4qNNV9mFLP FarerN88Za01dcEAzYbKZ8pcuMF6PHo7CxuYtFgXZwcid4XDZBCMHKugqSMPH4Y1MWgGbN9I88L B7CDzsLuoLmqRIB2wGwLF9IU5SP23RHpjQKawVCoL6CKpPCjr6LthNclRZ5nwwZ/zoeRU/9l+wN o89l2Nn02kwD55KN1lyO9s+vcUKNh6UUDLyi7LEA51A7xdxyy9OYbcH+3f7B5yGibtKnIUP39Gf Rp0wLLfNnbAU38oxfgg== X-Proofpoint-ORIG-GUID: dkyrCpkb3k-wBFV9hFYxXzTtbQx2CSpe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-02_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607020121 There is a confusion regarding the autoresume bit. Some verions of the QUSB2 PHY have it in the TEST1 register, while on the others it is a part of the TEST_CTRL register. When adding support for autoresume bit, the code attempted to simplify the handling of those registers, putting both registers to the TEST1 layout entry. In the end, ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98 (because platforms using that layout didn't use autoresume), while msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1 layout entry. Update the platform data to specify the register to be used for autoresume handling, define both TEST1 and TEST_CTRL registers and merge ipq6018_regs_layout and msm8996_regs_layout which become identical afterwards. Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM") Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 38 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 1109c480843e..ff3bc8fc2f18 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -131,6 +131,7 @@ enum qusb2phy_reg_layout { QUSB2PHY_PORT_TUNE5, QUSB2PHY_PORT_TEST1, QUSB2PHY_PORT_TEST2, + QUSB2PHY_PORT_TEST_CTRL, QUSB2PHY_PORT_POWERDOWN, QUSB2PHY_INTR_CTRL, }; @@ -164,19 +165,6 @@ static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), }; -static const unsigned int ipq6018_regs_layout[] = { - [QUSB2PHY_PLL_STATUS] = 0x38, - [QUSB2PHY_PORT_TUNE1] = 0x80, - [QUSB2PHY_PORT_TUNE2] = 0x84, - [QUSB2PHY_PORT_TUNE3] = 0x88, - [QUSB2PHY_PORT_TUNE4] = 0x8C, - [QUSB2PHY_PORT_TUNE5] = 0x90, - [QUSB2PHY_PORT_TEST1] = 0x98, - [QUSB2PHY_PORT_TEST2] = 0x9C, - [QUSB2PHY_PORT_POWERDOWN] = 0xB4, - [QUSB2PHY_INTR_CTRL] = 0xBC, -}; - static const unsigned int msm8996_regs_layout[] = { [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80, @@ -184,8 +172,9 @@ static const unsigned int msm8996_regs_layout[] = { [QUSB2PHY_PORT_TUNE3] = 0x88, [QUSB2PHY_PORT_TUNE4] = 0x8c, [QUSB2PHY_PORT_TUNE5] = 0x90, - [QUSB2PHY_PORT_TEST1] = 0xb8, + [QUSB2PHY_PORT_TEST1] = 0x98, [QUSB2PHY_PORT_TEST2] = 0x9c, + [QUSB2PHY_PORT_TEST_CTRL] = 0xb8, [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc, }; @@ -294,6 +283,7 @@ struct qusb2_phy_cfg { unsigned int mask_core_ready; unsigned int disable_ctrl; unsigned int autoresume_en; + bool autoresume_in_test_ctrl; /* true if PHY has PLL_TEST register to select clk_scheme */ bool has_pll_test; @@ -318,6 +308,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = { .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready = PLL_LOCKED, .autoresume_en = BIT(3), + .autoresume_in_test_ctrl = true, }; static const struct qusb2_phy_cfg msm8998_phy_cfg = { @@ -336,7 +327,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = { static const struct qusb2_phy_cfg ipq6018_phy_cfg = { .tbl = ipq6018_init_tbl, .tbl_num = ARRAY_SIZE(ipq6018_init_tbl), - .regs = ipq6018_regs_layout, + .regs = msm8996_regs_layout, .disable_ctrl = POWER_DOWN, .mask_core_ready = PLL_LOCKED, @@ -347,7 +338,7 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = { static const struct qusb2_phy_cfg qcs615_phy_cfg = { .tbl = qcs615_init_tbl, .tbl_num = ARRAY_SIZE(qcs615_init_tbl), - .regs = ipq6018_regs_layout, + .regs = msm8996_regs_layout, .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready = PLL_LOCKED, @@ -379,6 +370,7 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = { .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready = PLL_LOCKED, .autoresume_en = BIT(3), + .autoresume_in_test_ctrl = true, }; static const struct qusb2_phy_cfg sm6115_phy_cfg = { @@ -391,6 +383,7 @@ static const struct qusb2_phy_cfg sm6115_phy_cfg = { .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready = PLL_LOCKED, .autoresume_en = BIT(3), + .autoresume_in_test_ctrl = true, }; static const char * const qusb2_phy_vreg_names[] = { @@ -678,11 +671,16 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) /* enable phy auto-resume only if device is connected on bus */ if (qphy->mode != PHY_MODE_INVALID && cfg->autoresume_en) { - qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], - cfg->autoresume_en); + unsigned int reg; + + if (cfg->autoresume_in_test_ctrl) + reg = cfg->regs[QUSB2PHY_PORT_TEST_CTRL]; + else + reg = cfg->regs[QUSB2PHY_PORT_TEST1]; + + qusb2_setbits(qphy->base, reg, cfg->autoresume_en); /* Autoresume bit has to be toggled in order to enable it */ - qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], - cfg->autoresume_en); + qusb2_clrbits(qphy->base, reg, cfg->autoresume_en); } if (!qphy->has_se_clk_scheme) -- 2.47.3