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Thu, 02 Jul 2026 11:32:51 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b3c7ef5b3sm15704735c88.1.2026.07.02.11.32.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 11:32:51 -0700 (PDT) From: Imran Shaik Subject: [PATCH v5 00/19] clk: qcom: Add DISPCC and GPUCC support for the Qualcomm Shikra SoC Date: Fri, 03 Jul 2026 00:01:22 +0530 Message-Id: <20260703-shikra-dispcc-gpucc-v5-0-cc13826d4d5a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAH6uRmoC/33Qy2rDMBAF0F8xWldhJI1ky6v8R+nCeiUiDzuSY 1pC/r2KQ5tQnG4ujOAeDXMh2afoM2mrC0l+ijn2xzLIt4rYbXfceBpdmQkHrkAyQfM27lJHXcy DtXQznEuqILXlAjgESUpzSD7Ez1l9/7jPyZ/OBR/vjw+7rWYZuf6RNwVMw6Gk3e8y5aDRuxCCM NBOM/+3LBn7XWukrpZO1yhRoWondSuYLntq+8Mhjm2FAZFpBV5p5kRtmwYctxYAnQdljDTKOOm R3Dbfxjz26Ws+z8Tm1f+9xMQoUBmcqgVD1Rm+7nNenc7d/vb9qsTMTvyJ4s0yxQulpQi8QBCMe UGJB6WALVOiUIpZZjpRC+mbFxQ+U7hMYaEaDhgYcC0YW6Cu1+s3iF7A41gCAAA= X-Change-ID: 20260513-shikra-dispcc-gpucc-6f59c23020f5 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Brian Masney , Dmitry Baryshkov Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=U7uiy+ru c=1 sm=1 tr=0 ts=6a46aed5 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=3CZ3qO44dVgf1hZb4ZMA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: c-Nygwx8ilF4oO0DogBt6IxAe8EeiwVF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAyMDE5NSBTYWx0ZWRfXwxljrGohE/wG jPXmelTuFSVwyIhVQHXQ8ffEPPPAwnnxJJj2o3Z0+fwWUHdKTZtFHi/AYExW8MOhv3JLMDl73b5 cFHUYyfhEF3aA4bNLT1A5dl87C7wIV8uJrHu0zfLNaiCcOOk6xTcalKM8ePpg8kTi6rKCS855SL ZeEp3JjFehE9R2HTEqdkEhmLK5Vn+AsoDvSVDZmh34aHxIpc4RZhPWUZb7nKeIDji0IvNLjHjIs fG5DfkcHwKCt2BB2MhjKGbgIsHl4FKWl1xcJ/7FT5CscJ+EYa5cbdUWDmmnepuXAIJXMmi6hLhZ bh6SpvGkAlG9Q4wPYUV27SWc81A5/pmyXtBRByeW6CZonTdaddA8X/dEVekBWJCLDXvi8fab9el M4jSk4jaLNEwXRp3JlE/Hrm2xgp7xq7qo5bhRqjJ0Gf59PxnjTWWBVP/BdTGlynxq01ijzdaTJq ftkx+IaiPrSu9XT8t8A== X-Proofpoint-GUID: c-Nygwx8ilF4oO0DogBt6IxAe8EeiwVF X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAyMDE5NSBTYWx0ZWRfXwKsrUoUulzqL WnTD0XzpYCIGHSRWgSfzECG4NHYwRONIktwgIf0D/NNyMGPycMOud9IVjig4Xo6jjBiurQWrVLw wQcyTKEn2lzc/HDjpeILdb5vml4Ww1U= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-02_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607020195 This series adds support for the Display clock controller (DISPCC) and GPU Clock Controller (GPUCC) on Qualcomm Shikra SoC, by reusing the respective QCM2290 SoC drivers. This series extends the QCM2290 DISPCC bindings by adding support for the DSI1 PHY and sleep clock inputs, as well as the CX power rail. The Agatti device tree is updated accordingly to comply with the revised bindings. As a result, the existing DISPCC binding and corresponding DT ABI are changed, making this an ABI-breaking update. Shikra GCC series link: - https://lore.kernel.org/all/20260608-shikra-gcc-rpmcc-clks-v5-0-94cefe092ee3@oss.qualcomm.com/ Signed-off-by: Imran Shaik --- Changes in v5: - Collected all Reviewed-by tags received on v4. - Updated the commit text of the bindings patches [Krzysztof] - Converted only the critical GCC clocks to the latest clk_cbcr convention - Reorganize the series into logically independent patches [Krzysztof/Dmitry] - Added CX power domain support for DISPCC [Konrad] - Dropped DSI1 PHY clock input support from the driver, as these clocks are not referenced by any frequency table. - Link to v4: https://lore.kernel.org/r/20260604-shikra-dispcc-gpucc-v4-0-8204f1029311@oss.qualcomm.com Changes in v4: - Included new patch for Shikra DISPCC/GPUCC DT node support - Link to v3: https://lore.kernel.org/r/20260601-shikra-dispcc-gpucc-v3-0-61c1ba3735e8@oss.qualcomm.com Changes in v3: - Updated the QCM2290 GCC patch to use the .clk_cbcr convention - Extended the QCM2290 GPUCC bindings to add DSI1 PHY and Sleep clocks - Separated the patches as per the review comments in v2 series - Added Agatti DISPCC DT node changes as per the latest bindings changes - Link to v2: https://lore.kernel.org/r/20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com Changes in v2: - Dropped QCM2290 GCC critical clocks modelling to kept them ON from probe. - Updated the QCM2290 DISPCC/GPUCC bindings to align for Shikra drivers reuse. - Reused the QCM2290 DISPCC driver for Shikra without modernizing (keeping the clock-names approach) for now to avoid potential bindings ABI breakage. - Modernized QCM2290 GPUCC driver to use commmon qcom_cc_probe() model and reuse for Shikra. - Link to v1: https://lore.kernel.org/r/20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com --- Imran Shaik (19): clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe dt-bindings: clock: qcom,qcm2290-dispcc: Add DSI1 PHY and sleep clocks dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: dispcc-qcm2290: Switch to DT index based clk lookup clk: qcom: dispcc-qcm2290: Set HW_CTRL_TRIGGER flag for GDSC clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values clk: qcom: gpucc-qcm2290: Drop pm_clk handling clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra arm64: dts: qcom: agatti: Add DSI1 PHY and sleep clocks to DISPCC node arm64: dts: qcom: agatti: Add missing CX power domain to DISPCC arm64: dts: qcom: shikra: Add support for DISPCC/GPUCC nodes .../bindings/clock/qcom,qcm2290-dispcc.yaml | 35 ++++++- .../bindings/clock/qcom,qcm2290-gpucc.yaml | 4 +- arch/arm64/boot/dts/qcom/agatti.dtsi | 11 +- arch/arm64/boot/dts/qcom/shikra.dtsi | 42 ++++++++ drivers/clk/qcom/dispcc-qcm2290.c | 79 ++++++++------ drivers/clk/qcom/gcc-qcm2290.c | 113 +++------------------ drivers/clk/qcom/gpucc-qcm2290.c | 102 ++++++++----------- 7 files changed, 190 insertions(+), 196 deletions(-) --- base-commit: 4f441960e691d37c880d2cc004de06bb5b6bd5e4 change-id: 20260513-shikra-dispcc-gpucc-6f59c23020f5 prerequisite-change-id: 20260429-shikra-gcc-rpmcc-clks-2094edfff3b0:v5 prerequisite-patch-id: 59bb0a7828e41f546f734f127d81da83c0adcda9 prerequisite-patch-id: 197da6bcb15cadc47869dba88c8020987b25c335 prerequisite-patch-id: 8ec9c1eb03f052ae232ed54117abed38672c23f6 prerequisite-patch-id: 350db4f4bcdfc0fad9ed57cd5b1723f85ad44f5d prerequisite-change-id: 20260511-shikra-dt-d75d97454646:v6 prerequisite-patch-id: 3a689e8dda5fd2755b689d94d095806b3f2e6eed prerequisite-patch-id: ac83151a889855498d36288ddd36216d451340c8 prerequisite-patch-id: 2357cac636e019eaf14d6a493a1c72bca56fe405 prerequisite-patch-id: 2885f299e711582da312ca9d13983d296a3dd5dc prerequisite-patch-id: 91af5f3c01e766a53ce8de69aa21847a2d6bbbf8 Best regards, -- Imran Shaik