From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 975483921CD for ; Fri, 3 Jul 2026 06:52:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783061543; cv=none; b=XWmm3S32tooJpzqwVzb8plDnJVeAwLlgpa+Hofz4q/eXwPJlQWJndtvXhfIOFO8vInLiHJWSLmaN24au6BBbdUfGrbW4LhZgePlGSExZ5e8Peuk1OJ1ia0gjg8teEU6yi7S/2ev/zYVaBAm3wbN9dyidfXmR+/1yD7nPuAfvdz8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783061543; c=relaxed/simple; bh=R7p0EC1MJExELMNko6n8EU7bwP08zWcgCr3KfDmFr5g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bw1Zl+2hCoAdwNiA/++eMo7f1KZ7HbuD02/qRtPqiVPPTEqmNQlw4B47aAmrXv5V0hqUiGpmqyB+WAvdp4unpbJy6XqtVNllsPyuRe7HKGeb2jFXdTuzaEK1n9qD2OePOIkcwfB3FH+hgSZVoxwg/NHqaYx2w0Sdwpymrin6uO0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=JjJDaNh2; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="JjJDaNh2" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-c128cc012b4so33648966b.1 for ; Thu, 02 Jul 2026 23:52:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1783061540; x=1783666340; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ehG0wNhXC7EZrYAkm3RwKsx8ZO4vZ8QiozKkc4jo0Cw=; b=JjJDaNh2lNLBo10eFgcXKp0iAwMgrQXS2XqOEyNjIzR6GUpjunsXqVW4x1T45DKtWV QJAWM0ezMv/PUoR6v2AcAJ4LtDgARCzbdM+OJXcIceI1PJ78BFF+Rb5lMemjY/Fr3f7K 7Ui7Tg0MNDK4W6ZLKxCjDR9AWXA0ghNqHzxvY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783061540; x=1783666340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ehG0wNhXC7EZrYAkm3RwKsx8ZO4vZ8QiozKkc4jo0Cw=; b=nxceCuKxnbQFUZMqRr0rcv6wddWJ7htnqw9ohsOJ1iccNDP2JMlT0Ivb3luImR4Cqm /2jvxtG1nqb5KnFeo2nGJHmExcBaBaT6k7ZG5M+Ww704LJFKB2K3IvT2LpfLVT/RIoBI QG4yYWSVyH4KB244chClgWsYusFf4HPkV9jZ3JnP6pAX3hh6GxcQ+eT/1MLFsS/mW/ID 9EyFWvrsH2vPQyPt7B88RJ/U2hz0s6z0QdB2DvWm/o9AB1E5SNyhP1YelHGqJA/C+1V0 Q/IdmxN1UI61hXo5m+lNuU0/jwiuhqO5s9SjG+aEL3Wnb5J9HWvbwkaiItvyg7N9lIq8 2WnQ== X-Gm-Message-State: AOJu0Yz5YHUNjkiDVv579upo7GwZWKNE1YnxbDqbX18EEZ/LiCpRZS7d yVkTLc31/dAkvhjXSc1lLFvrnZk8qSUMdaLKblwBXzZb8Ovmd8eY3CUF1ngwOWvUceRKpLeXvWS tJhCutP4= X-Gm-Gg: AfdE7cmPIOkQ211t/skR0quQau4mdU/tqJh91SG0zUuECSB4G0SIMPxpHAmdqzlgsCz kxUeV7CtwfHrBTj2K9KMW4J6tq1nOSI4ZmYxLlCvC8X5rZ7kIUeu6CsHIdHJBQe616u+AF7mkJN V+we6kid0yWNmmqJljIITkHjtW9CMTD5gUH/o4C/kccFjWc9ozL8qkKz1KuXtb33Brlkwn3Hv4L ZrIYg9QdhJV4ZUWD13qbIOVaRIGfm/qoI3KxO1+34t6bxuvnInLXeJSF6ewcfLq/7wZRY6urDu5 /SkAp28NiXXutzVrHKQUghk1XwypQm0JcdTnflW4jWh7AWLd+DG147zlfTHK3GsY8PTge3x6+Qk 6Rke0ca8F+3jfrHXOIW++NpQ0qi/rg13vvttfgqCd76QR63CDnfNn8Khoq5hjwwAftctFw/0Ani 89HM013XZFpv1NrMg3QJ9cYA3QXhh90dml0QHYHTJP/iOow0bIZqlQw/EqydQUmTE//wLY4pGzR vgSm3riVcU= X-Received: by 2002:a17:907:a394:b0:c12:5ac7:b346 with SMTP id a640c23a62f3a-c12c9fb521fmr113023766b.21.1783061539868; Thu, 02 Jul 2026 23:52:19 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.. ([2.196.43.95]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c12b62c4695sm235462866b.44.2026.07.02.23.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 23:52:18 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v7 14/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM Date: Fri, 3 Jul 2026 08:49:04 +0200 Message-ID: <20260703065110.1433283-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com> References: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Support Engicam MicroGEA-STM32MP257 SoM with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM The SoM also provides an Ethernet MAC, but Ethernet support is not enabled at this stage due to a known silicon limitation documented in [1]. This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC errors"), where CRC errors may occur in ETH1 RMII direct mode when directly connected to I/Os. The workaround requires use of the Ethernet switch (ETHSW), which introduces additional DT bindings and topology complexity. This is intended to be addressed in a separate patch series. [1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Drop inclusion of stm32mp25xf.dtsi, we are using stm32mp257d. Changes in v3: - Fix a typo in the URL .../dts/st/stm32mp257-engicam-microgea.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi new file mode 100644 index 000000000000..5b4287e86def --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "Engicam MicroGEA STM32MP257 SoM"; + compatible = "engicam,microgea-stm32mp257", "st,stm32mp257"; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vddcore: regulator@b { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@e { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@10 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd3v3_usb: regulator@14 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&scmi_v3v3>; + vqmmc-supply = <&scmi_vddio2>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; -- 2.43.0