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Fri, 03 Jul 2026 01:34:45 -0700 (PDT) Received: from hu-raviravi-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30f0b7b9a8asm18797839eec.2.2026.07.03.01.34.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2026 01:34:45 -0700 (PDT) From: Ravi Hothi To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mohammad.rafi.shaik@oss.qualcomm.com, ajay.nandam@oss.qualcomm.com Subject: [PATCH v1 1/2] arm64: dts: qcom: eliza: Add LPASS macro and SoundWire support Date: Fri, 3 Jul 2026 14:04:20 +0530 Message-Id: <20260703083421.2736184-2-ravi.hothi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260703083421.2736184-1-ravi.hothi@oss.qualcomm.com> References: <20260703083421.2736184-1-ravi.hothi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAzMDA4MSBTYWx0ZWRfX9Sf0DnGM4myV E8UWaYLF51gTGz1MKaCzt9zTp+Nf+Brg4AIZmI5zHHMulsiwXTbAmyLrKdrds4ks24bzYIQaJSt 1YahhRGdXrEbyM6EnaJQ2cn/BJ8ECRs= X-Proofpoint-ORIG-GUID: ADBSTbAm8AYwm5jGqYZbqhVMZSKow8Hs X-Authority-Analysis: v=2.4 cv=O4wJeh9W c=1 sm=1 tr=0 ts=6a477427 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=hg4zlKkQFggHIW0abPEA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: ADBSTbAm8AYwm5jGqYZbqhVMZSKow8Hs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAzMDA4MSBTYWx0ZWRfX/2BuAN/jTMRe dAE3b0ZFmzsa477k+5mygUjqBwLWRuOV3R0GJXyeK5xhq3j8VSrQSH+fqRt9YPa0HdkA+Y5K2TP 3OmJ1vakkZFygzEzPHnQS486FmHdn1h9Uv3YbS19AvNxZL1LviVOh4ZgZr+2qz1hU6JSmR6A/Ni wd6TMjpGjHH/CJG63FWZCQfKZZNW+Xj7ETalPFrG0DZUT/t5n47GgrwNt7EOhSAyoXmuAwQDRr7 1TETjCHVJDPyupDx0/aIMdy0C0W7xlTdP7Iq2htu8rFz9qTvtQ1lXYaQ/Mvomdriylifz4madXv ey+bc5J/i+iv9789mcQDstzKTapsR1nLP1adPUuH3xmaEIJFrjAfC/OzybH4lVeKzDmh1EM8b6o ztuMeMPnkrZEka06Rp2eJwhAxRdJZcrTPDLBqvuD0wYY2vwD5G6NZ/TR3pNbbtYs2Z1wvIuyJ1B TncrWl+TyiVdLhdg+yg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-03_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 phishscore=0 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607030081 Add SoC-level LPASS WSA macro, VA macro, SoundWire controller and LPASS LPI pin controller nodes. DMIC and WSA SoundWire pinctrl states are defined inside the LPASS LPI pin controller node. The hardware is similar to the SM8750 platform. The WSA macro, VA macro and SoundWire controller are kept disabled so board DTS files can selectively enable and configure them. Signed-off-by: Ravi Hothi --- arch/arm64/boot/dts/qcom/eliza.dtsi | 193 ++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 8dbfd0504598..142f43a1e6a3 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -2072,6 +2073,198 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,eliza-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06b00000 0x0 0x1000>; + + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + swr0: soundwire@6b10000 { + compatible = "qcom,soundwire-v2.1.0", + "qcom,soundwire-v2.0.0"; + reg = <0x0 0x06b10000 0x0 0x10000>; + interrupts = ; + + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + + label = "WSA"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = + /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f + 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = + /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 + 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = + /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f + 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = + /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 + 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + lpass_vamacro: codec@7660000 { + compatible = "qcom,eliza-lpass-va-macro", + "qcom,sm8550-lpass-va-macro"; + reg = <0x0 0x07660000 0x0 0x2000>; + + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible = "qcom,eliza-lpass-lpi-pinctrl"; + reg = <0x0 0x07760000 0x0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic45_default: dmic45-default-state { + clk-pins { + pins = "gpio12"; + function = "dmic3_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio13"; + function = "dmic3_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic67_default: dmic67-default-state { + clk-pins { + pins = "gpio21"; + function = "dmic4_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio22"; + function = "dmic4_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + sdhc_2: mmc@8804000 { compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x08804000 0x0 0x1000>; -- 2.34.1