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Sun, 05 Jul 2026 12:14:14 -0700 (PDT) From: Anna Maniscalco Date: Sun, 05 Jul 2026 21:13:35 +0200 Subject: [PATCH RFC 01/13] iommu: arm-smmu-qcom: Configure lpac device with split address space Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260705-descriptive-name-lpac-upstream-v1-1-01d50c3e0c99@gmail.com> References: <20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com> In-Reply-To: <20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Anna Maniscalco X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783278851; l=2198; i=anna.maniscalco2000@gmail.com; s=20240815; h=from:subject:message-id; bh=TOpopsFtZ1PPnGuz7Qdse1Rb2dSOsjvazts1+j2Qsuk=; b=swnPSg6jJwnfwPpO2lUtsliGm7jHo9gqL51QEmCML+oAIm1zPDuCFHYdt3TNVGcjeXVx38cVC 13fGjbA8BMDAB0TZwyRx8GCJenaSAUzrSU2r89a5X2KYaRbtynBvrSe X-Developer-Key: i=anna.maniscalco2000@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= We want the context bank used by LPAC to use split address space just like GFX. Signed-off-by: Anna Maniscalco --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index edd41b5a3b6a..48a590aaeb5e 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -35,6 +35,8 @@ static const struct of_device_id qcom_smmu_actlr_client_of_match[] = { { .compatible = "qcom,adreno", .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, + { .compatible = "qcom,lpac", + .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, { .compatible = "qcom,adreno-gmu", .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, { .compatible = "qcom,adreno-smmu", @@ -217,6 +219,7 @@ static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_a } #define QCOM_ADRENO_SMMU_GPU_SID 0 +#define QCOM_ADRENO_SMMU_LPAC_SID 1 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) { @@ -230,7 +233,8 @@ static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) for (i = 0; i < fwspec->num_ids; i++) { u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); - if (sid == QCOM_ADRENO_SMMU_GPU_SID) + if (sid == QCOM_ADRENO_SMMU_GPU_SID || + sid == QCOM_ADRENO_SMMU_LPAC_SID) return true; } @@ -305,9 +309,9 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma */ if (qcom_adreno_smmu_is_gpu_device(dev)) { start = 0; - count = 1; + count = 2; } else { - start = 1; + start = 2; count = smmu->num_context_banks; } @@ -394,6 +398,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,adreno" }, + { .compatible = "qcom,lpac" }, { .compatible = "qcom,adreno-gmu" }, { .compatible = "qcom,glymur-mdss" }, { .compatible = "qcom,mdp4" }, -- 2.54.0