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Sun, 05 Jul 2026 12:14:36 -0700 (PDT) From: Anna Maniscalco Date: Sun, 05 Jul 2026 21:13:46 +0200 Subject: [PATCH RFC 12/13] drm/msm: set ctxbank and asid based on ring Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260705-descriptive-name-lpac-upstream-v1-12-01d50c3e0c99@gmail.com> References: <20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com> In-Reply-To: <20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Anna Maniscalco X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783278851; l=1658; i=anna.maniscalco2000@gmail.com; s=20240815; h=from:subject:message-id; bh=GNmboLcpB1u+4sbu+20YXtJhFgR6gBIC5iE7jNeRoQc=; b=rmC2QQUsBeGBctekJrkX9Bu4XpWytNrOy081NaDsxEdKs3EL5tzPk65CpjizWt1u9+G71Ip0Z pqDS3aq7HVdCwtuw5G8Lc0fcU6h3n5cTjmCTycxplXu/JrouOa8zMbf X-Developer-Key: i=anna.maniscalco2000@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= qcom-arm-smmu always maps asid and ctxbank 1:1 and lpac is always 1 Signed-off-by: Anna Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 4417a9d04d7c..a8a061652ec2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -247,7 +247,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; phys_addr_t ttbr; bool is_lpac = ring == a6xx_gpu->base.base.lpac_rb; - u32 asid; + u32 asid, ctxbank; u64 memptr = rbmemptr(ring, ttbr0); if (ctx->seqno == ring->cur_ctx_seqno) @@ -256,6 +256,9 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, if (msm_iommu_pagetable_params(to_msm_vm(vm)->mmu, &ttbr, &asid)) return; + /* qcom-arm-smmu always maps asid and ctxbank 1:1 */ + ctxbank = asid = is_lpac; + if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) { /* Wait for previous submit to complete before continuing: */ OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); @@ -313,7 +316,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | CP_SMMU_TABLE_UPDATE_1_ASID(asid)); OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); - OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); + OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(ctxbank)); /* * Write the new TTBR0 to the memstore. This is good for debugging. -- 2.54.0