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Sun, 05 Jul 2026 12:14:38 -0700 (PDT) From: Anna Maniscalco Date: Sun, 05 Jul 2026 21:13:47 +0200 Subject: [PATCH RFC 13/13] drm/msm: add lpac ring to devcoredump Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260705-descriptive-name-lpac-upstream-v1-13-01d50c3e0c99@gmail.com> References: <20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com> In-Reply-To: <20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Anna Maniscalco X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783278851; l=2731; i=anna.maniscalco2000@gmail.com; s=20240815; h=from:subject:message-id; bh=wmCqgt9bbc7y6girDLeQUG/lasgVe98klmVzcoHOM/o=; b=PVK05TezP6oByIlmJqXX6RCKZc0Sfa+FvqbaJD2D2MNQt18wh5zplyqPzMUoPj4wq2v3x/AHS ORhKtsBbYDeCcbFNugaM2rR3PLhNr8TrJkg/x8sEhnkPAzo9vnVPIw+ X-Developer-Key: i=anna.maniscalco2000@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Add the LPAC ring state to the devcoredump for debugging. Signed-off-by: Anna Maniscalco --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++++--------- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 94dbec9464a4..030bb1aeb7ee 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -782,25 +782,26 @@ int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) ktime_get_real_ts64(&state->time); - for (i = 0; i < gpu->nr_rings; i++) { + for (i = 0; i < gpu->nr_rings + !!gpu->lpac_rb; i++) { + struct msm_ringbuffer *ring = i < gpu->nr_rings ? gpu->rb[i] : gpu->lpac_rb; int size = 0, j; - state->ring[i].fence = gpu->rb[i]->memptrs->fence; - state->ring[i].iova = gpu->rb[i]->iova; - state->ring[i].seqno = gpu->rb[i]->fctx->last_fence; - state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); - state->ring[i].wptr = get_wptr(gpu->rb[i]); + state->ring[i].fence = ring->memptrs->fence; + state->ring[i].iova = ring->iova; + state->ring[i].seqno = ring->fctx->last_fence; + state->ring[i].rptr = get_rptr(adreno_gpu, ring); + state->ring[i].wptr = get_wptr(ring); /* Copy at least 'wptr' dwords of the data */ size = state->ring[i].wptr; /* After wptr find the last non zero dword to save space */ for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) - if (gpu->rb[i]->start[j]) + if (ring->start[j]) size = j + 1; if (size) { - state->ring[i].data = kvmemdup(gpu->rb[i]->start, size << 2, GFP_KERNEL); + state->ring[i].data = kvmemdup(ring->start, size << 2, GFP_KERNEL); if (state->ring[i].data) state->ring[i].data_size = size << 2; } @@ -1001,7 +1002,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_puts(p, "ringbuffer:\n"); - for (i = 0; i < gpu->nr_rings; i++) { + for (i = 0; i < gpu->nr_rings + !!gpu->lpac_rb; i++) { drm_printf(p, " - id: %d\n", i); drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); drm_printf(p, " last-fence: %u\n", state->ring[i].seqno); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 263dafeb9652..4fbf0dedc334 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -639,7 +639,7 @@ struct msm_gpu_state { void *data; int data_size; bool encoded; - } ring[MSM_GPU_MAX_RINGS]; + } ring[MSM_GPU_MAX_RINGS+1]; int nr_registers; u32 *registers; -- 2.54.0