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Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260706-a733-rtc-v4-8-f330728db3d3@baylibre.com> References: <20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com> In-Reply-To: <20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com> To: Junhui Liu , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2479; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=mDE5aNV7J0YTDC++0PyqpQq+1LRXe/OEq5dNJJriQq0=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBqS3YmTWLBuAgutDebw3ejtGqAFUPS56EkSWc4A wtGJpbqBNSJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCakt2JgAKCRDm/A8cN/La hVRZD/9c7MLYh8cPg12ioyQi+NhtPqzROV5AnuK4OgtAmpPfUuF85geQbj6t5HzciSP2Hh5Mc07 aeHHxl1ymAujhPPVz/w0sx4tnU+MQcTN0E/JoNe6YjsD4IXSKB2UYWaz2Mzj2rHOBpz8Jt9BdFc UQ+FcbGsS1mwn9pQK5kgnb/qp6qptHo5Kz/Rih4Zsnx17p0P6tn0hMHPUa1KSiBattQ0RX+xAt2 IWtiahvXeBrLgJyzYxnMeK70V8BtmwhBIPs1dFcCzFka/fKigZrksQx8e7ZsF0AUqwkcbbSdIRT ZCd3xtLzkBr1JoH/pO9xhIl3YI4eAPZVc/jnTc1DfSNmnrplpCz3KKensHb+1OJgpT9r0h84CTP c+cJ1JLw3U1lLEzIaDO8qd6WKjb6zIHaifi0TOp+L/JZ+HHGvyCaSc5Dq2tD7PGFpfwEVAMH3xZ tL8TXrkKZuCXaxuOJNB7N3lFLcqjU/0C+Xi7RdoDJZDZ8p4ARlcQYEC6p/16tVFuvRWgKI7cEIL mwOOfAGoQLdeKsNPTFgA5qOjVVZNIn24USq7nNhqzvmSXlZvTBpSswK5YjYXGrCCO79jPg3hdwR POG1wdQfq4QO6f7JNq1s/CJgCpm662359uW9sY5QIdpPDl+Uui0d9y7VRYZHOHWijGo6fR3pkgT ySkhTV0XZ+V7+gQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 On the a733 the "osc24M-32k" clock has the same gate bits as the previously supported SoC but a different divider implementation. Instead of a fixed 750 divider, the divider is selected based on the rate of the oscillator. It can be seen as a simple read-only divider. To easily replace the divider part depending the SoC, split the divider and gate into two separate clock entities. Signed-off-by: Jerome Brunet --- drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 20 +++++++++++--------- drivers/clk/sunxi-ng/ccu-sun6i-rtc.h | 3 ++- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c index b24c8b196e66..25dd87e78eb7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -218,17 +218,18 @@ static const struct clk_parent_data osc24M[] = { { .fw_name = "hosc", .name = "osc24M" } }; -static struct ccu_gate osc24M_32k_clk = { - .enable = BIT(16), - .common = { - .reg = LOSC_OUT_GATING_REG, - .prediv = 750, - .features = CCU_FEATURE_ALL_PREDIV, - .hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k", osc24M, - &ccu_gate_ops, 0), - }, +static struct clk_fixed_factor osc24M_32k_div_clk = { + .mult = 1, + .div = 750, + .hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div", + osc24M, + &clk_fixed_factor_ops, + 0), }; +static SUNXI_CCU_GATE_HW(osc24M_32k_clk, "osc24M-32k", &osc24M_32k_div_clk.hw, + LOSC_OUT_GATING_REG, BIT(16), 0); + static const struct clk_hw *rtc_32k_parents[] = { &osc32k_clk.common.hw, &osc24M_32k_clk.common.hw @@ -286,6 +287,7 @@ static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = { [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, [CLK_RTC_32K] = &rtc_32k_clk.common.hw, + [CLK_OSC24M_32K_DIV] = &osc24M_32k_div_clk.hw, }, }; diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h index 9ae821fc2599..ab7b92b47f59 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h @@ -9,7 +9,8 @@ #define CLK_EXT_OSC32K_GATE 4 #define CLK_OSC24M_32K 5 #define CLK_RTC_32K 6 +#define CLK_OSC24M_32K_DIV 7 -#define CLK_NUMBER (CLK_RTC_32K + 1) +#define CLK_NUMBER (CLK_OSC24M_32K_DIV + 1) #endif /* _CCU_SUN6I_RTC_H */ -- 2.47.3