From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F7AE47ECE8; Mon, 6 Jul 2026 23:06:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783379191; cv=none; b=iEk/nio7j/8u9rzquI1n5Mcm4VQfuYjfNcD8rTDIKrZkDst2VdwGhmRlL61+WE4ROlXwh6KlcOPUibCT+Yoc+DICVvUdf0+iTcApsqJC2IDb9PrPCgRpvLtZ1GdP8329rPZTwyjAtOQcZ9VxwqO8X33AunujWm+hadi+NHvswD4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783379191; c=relaxed/simple; bh=/lHu3eVAuHsLEigeHCp+bZ6GY4SmlXtvbvnXYPzk0WA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fLrBuGnZtoYLF+ezkDYQZZP/D8S2JB+FT2ZE4QZ7hWr77QCyhhMHlTsMOWdIDFYaShfUEXDUB+y7DUe4iIkx5ivS4PsjyG6eNyXMzUnXv2I0fqub5tqU6MnY8rUHh1/9u/Wlxx7PNCMlVDUO/565gLlMvNVqqsnE0Z9cDo2DFU0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WgGJHgDO; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WgGJHgDO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95A191F00ADB; Mon, 6 Jul 2026 23:06:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783379189; bh=lHAGvQs3Wz49nHzEJXNVSBn/1UzBTGfY8mMrzsLceis=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=WgGJHgDOBsODtDixM5GLJe8Pz2R2rwGSr73n6lkAGGhCg0hOmDHGFupVj2Ei+DxLI j3kd56fxIQsQOI46Ys+U2UjrFbPnViBLIP9XYtuQ7KPkvJ/yt4ehYwLQCAnTLvUaxP LowaPvHrl1jeL81WMCox712hkiTRh9+pi+tuOH9Nq6Qu9FQvr6Ki/NkIkbUg5uOUsj hYIUdWVhuREgacJgPOH+666IdQoO10dfsaJu69yTID4OkQ5bIDI2odxqDFuCA15wN8 Q+NvoRXDtdeO1jbzVdG0XJbyIOk9e9Ym6QXiyrOIe8HGZwQeiQqn8SA1hnnaA/hf68 MlC+SuIO+RBbQ== From: Drew Fustini Date: Mon, 06 Jul 2026 16:06:17 -0700 Subject: [PATCH v4 7/8] dt-bindings: riscv: Add binding for CBQRI controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260706-dfustini-atl-sc-cbqri-dt-v4-7-e75c20201d64@kernel.org> References: <20260706-dfustini-atl-sc-cbqri-dt-v4-0-e75c20201d64@kernel.org> In-Reply-To: <20260706-dfustini-atl-sc-cbqri-dt-v4-0-e75c20201d64@kernel.org> To: Adrien Ricciardi , Alexandre Ghiti , Atish Kumar Patra , Atish Patra , Babu Moger , Ben Horgan , Borislav Petkov , Chen Pei , Conor Dooley , Conor Dooley , Dave Hansen , Dave Martin , Fenghua Yu , Gong Shuai , Gong Shuai , guo.wenjia23@zte.com.cn, James Morse , =?utf-8?q?Kornel_Dul=C4=99ba?= , Krzysztof Kozlowski , liu.qingtao2@zte.com.cn, Liu Zhiwei , Palmer Dabbelt , Paul Walmsley , Peter Newman , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Reinette Chatre , Rob Herring , Samuel Holland , Sebastian Andrzej Siewior , Tony Luck , Vasudevan Srinivasan , Ved Shanbhogue , Weiwei Li , yunhui cui , Drew Fustini Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, devicetree@vger.kernel.org, linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4724; i=fustini@kernel.org; h=from:subject:message-id; bh=/lHu3eVAuHsLEigeHCp+bZ6GY4SmlXtvbvnXYPzk0WA=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWT5mHx4s+uizN45z16zHUzwCd+k8j72e+C7754i0+2fu R/XX5jyq6OUhUGMi0FWTJFl04e8C0u8Qr8umP9iG8wcViaQIQxcnAIwkXO6DP+DP+94IBJ19MD2 QyHupz/nr6jkaJQKyxNY2ffvRIryqq9eDP/U57zcyJ43/bvgeW7frJrSp7dmevw6tI7DZnWPsho fzyUmAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Document the device tree binding for RISC-V CBQRI capacity and bandwidth controllers. Each controller is named by a device-specific compatible followed by the generic compatible. The binding also describes the common riscv,cbqri-rcid and riscv,cbqri-mcid properties, and the optional riscv,cbqri-cache phandle that links a capacity controller to the cache whose capacity it allocates. Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Conor Dooley Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- .../devicetree/bindings/riscv/riscv,cbqri.yaml | 97 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 98 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml new file mode 100644 index 000000000000..62d547a0cb96 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/riscv,cbqri.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI) controller + +description: | + The RISC-V CBQRI specification defines capacity-controller and + bandwidth-controller register blocks that allocate cache capacity and memory + bandwidth to resource-control IDs (RCIDs) and monitor usage per + monitoring-counter ID (MCID): + https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf + + Allocation and monitoring share one register block, and a controller may + implement either or both. A driver discovers which at runtime from the + capabilities register, so the compatible names only the controller type. It + does not distinguish allocation-only, monitoring-only or combined + controllers, and no property declares monitoring support. + +maintainers: + - Drew Fustini + +properties: + compatible: + oneOf: + - items: + - enum: + - tenstorrent,ascalon-shared-cache-controller + - const: riscv,cbqri-capacity-controller + - items: + - {} + - const: riscv,cbqri-bandwidth-controller + + reg: + maxItems: 1 + description: + The CBQRI controller register block. + + riscv,cbqri-rcid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum number of RCIDs the controller supports. RCIDs are the + resource-control IDs that allocation operations target. + + riscv,cbqri-mcid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum number of MCIDs the controller supports. MCIDs are the + monitoring-counter IDs that usage-monitoring operations target. Present + on controllers that implement monitoring. + + riscv,cbqri-cache: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the cache node whose capacity this controller allocates. + Applies to capacity controllers that back a CPU cache. The cache level + and the harts sharing it are taken from that node's cache topology. + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: tenstorrent,ascalon-shared-cache-controller + then: + required: + - riscv,cbqri-rcid + - riscv,cbqri-cache + +additionalProperties: false + +examples: + - | + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + cache-sets = <512>; + cache-block-size = <64>; + }; + + qos-controller@a21a00c0 { + compatible = "tenstorrent,ascalon-shared-cache-controller", + "riscv,cbqri-capacity-controller"; + reg = <0xa21a00c0 0xf40>; + riscv,cbqri-rcid = <16>; + riscv,cbqri-cache = <&l2_cache>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index c11696c4be66..5898fbcf4e2f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23343,6 +23343,7 @@ M: Drew Fustini R: yunhui cui L: linux-riscv@lists.infradead.org S: Supported +F: Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml F: arch/riscv/include/asm/qos.h F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos.c -- 2.43.0