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Mon, 06 Jul 2026 09:56:58 -0700 (PDT) Received: from hu-bibekkum-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c9e8eb0efc8sm6960604a12.5.2026.07.06.09.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2026 09:56:57 -0700 (PDT) From: Bibek Kumar Patro Date: Mon, 06 Jul 2026 22:26:35 +0530 Subject: [PATCH v3 2/6] iommu/arm-smmu: Add interconnect bandwidth voting support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260706-smmu_interconnect_addition-v3-2-afdca0125a65@oss.qualcomm.com> References: <20260706-smmu_interconnect_addition-v3-0-afdca0125a65@oss.qualcomm.com> In-Reply-To: <20260706-smmu_interconnect_addition-v3-0-afdca0125a65@oss.qualcomm.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bibek Kumar Patro X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783357002; l=8198; i=bibek.patro@oss.qualcomm.com; s=20260617; h=from:subject:message-id; bh=lat7Bx/Hq+cGZXWIYs7lxJhgcpijDQh+OJ5u9DwkhsI=; b=nAo1SdSTHRgHqoWATvufzYzKXA6ZSzlLu/yclNPZ/Su18G0rQKinCdWabI3CJGi0YHltUYo5y O9zxAukcXszCKTXclXBkKXSAOAvDyoEonRQeqlyX4jAe0fn3JicK1Zr X-Developer-Key: i=bibek.patro@oss.qualcomm.com; a=ed25519; pk=DkrbE5dhskZJmBAKR5LygWRsAydEOSN+T0/YxNYxDLM= X-Proofpoint-ORIG-GUID: Jw_MBVmonhfo8Oh4BAqJ-GpWSzdlJSmR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDE3MCBTYWx0ZWRfX+Meje0z7F5yV 5irFdQ7bk7gdNMIDyUw6kOpazChCJBY45KWrUzDWQ9xcrzYFnIBUS/ccdpJzaQwves8jMsOG0ap PDsANLRMV7wKPWy307dIP/LBuNWGGMME+/amP3CU40AKmH4re8MHoymNcTFHTpjiVxTB/G/APnE IPJET9rUiT7fkLfpWgFatHoAwLBqKmk4XCqeRGgbn4jJvdxpu6txwSchtrU+olSxVlGOqHJqYPe exU3Og3uG4IicVY8lo0CAuhyCW4+xMtYMTauEJBDEIXKfcxkKCyvq0hTnexQkxLXBtRNKROkNBn IqOqHJUVdaziu1OK0IZdVoGfqbn3GOVNYEt/oJ3Xjnne4PtVurvixF59w/QzUXqwpY0anpo5VYP wyoJ1dIkKvLMgCv4lT6A6lpZNtO6pK++twKHCtbqG1jOlnvWicgtgmf83phYDJA6C6MedStwV+G SwzrTsuNwcvna87sAEA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDE3MCBTYWx0ZWRfX/pmkT8Gvd0Ea Fu9/YZXQVDnePLC6iImq4I7ns6Smq2bTF4FyaS2AorqO3oKmXXUz5r2+MpPfBfmszXfbovKg4GB Cqng6dBlOvgHXY7TevlwO0pYuQOJfns= X-Authority-Analysis: v=2.4 cv=XIwAjwhE c=1 sm=1 tr=0 ts=6a4bde5b cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=EBvdZ6k9WR3IvNukGaMA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: Jw_MBVmonhfo8Oh4BAqJ-GpWSzdlJSmR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_02,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060170 On some SoCs the SMMU registers require an active interconnect bandwidth vote to be accessible. While other clients typically satisfy this requirement implicitly, certain corner cases (e.g. during sleep/wakeup transitions) can leave the SMMU without a vote, causing intermittent register access failures. Add support for an optional interconnect path to the arm-smmu driver and vote for bandwidth while the SMMU is active. The path is acquired from DT if present and ignored otherwise. The bandwidth vote is enabled before accessing SMMU registers during probe and runtime resume, and released during runtime suspend and on error paths. Generally, from an architectural perspective, GEM_NOC and DDR are expected to have an active vote whenever the adreno_smmu block is powered on. In most common use cases, this requirement is implicitly satisfied because other GPU-related clients (for example, the GMU device) already hold a GEM_NOC vote when adreno_smmu is enabled. However, there are certain corner cases, such as during sleep/wakeup transitions, where the GEM_NOC vote can be removed before adreno_smmu is powered down. If adreno_smmu is then accessed while the interconnect vote is missing, it can lead to the observed failures. Because of the precise ordering involved, this scenario is difficult to reproduce consistently. (also GDSC is involved in adreno usecases can have an independent vote) Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 55 +++++++++++++++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 3 ++ drivers/iommu/arm/arm-smmu/arm-smmu.c | 27 +++++++++++++-- drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ 4 files changed, 84 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index e2c914fccd6f..5133d3ab023a 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -607,6 +608,45 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) return ret; } +static int qcom_adreno_smmu_icc_init(struct arm_smmu_device *smmu) +{ + struct qcom_smmu *qsmmu = container_of(smmu, struct qcom_smmu, smmu); + int err; + + qsmmu->icc_path = devm_of_icc_get(smmu->dev, NULL); + if (!IS_ERR(qsmmu->icc_path)) + return 0; + + err = PTR_ERR(qsmmu->icc_path); + + if (err == -ENODEV) { + qsmmu->icc_path = NULL; + return 0; + } + return dev_err_probe(smmu->dev, err, + "failed to get interconnect path\n"); +} + +static int qcom_adreno_smmu_runtime_resume(struct arm_smmu_device *smmu) +{ + struct qcom_smmu *qsmmu = container_of(smmu, struct qcom_smmu, smmu); + int ret; + + ret = icc_set_bw(qsmmu->icc_path, 0, 1); + WARN_ON_ONCE(ret); + return ret; +} + +static int qcom_adreno_smmu_runtime_suspend(struct arm_smmu_device *smmu) +{ + struct qcom_smmu *qsmmu = container_of(smmu, struct qcom_smmu, smmu); + int ret; + + ret = icc_set_bw(qsmmu->icc_path, 0, 0); + WARN_ON_ONCE(ret); + return ret; +} + static const struct arm_smmu_impl qcom_smmu_v2_impl = { .init_context = qcom_smmu_init_context, .cfg_probe = qcom_smmu_cfg_probe, @@ -648,6 +688,8 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync, + .runtime_resume = qcom_adreno_smmu_runtime_resume, + .runtime_suspend = qcom_adreno_smmu_runtime_suspend, .context_fault_needs_threaded_irq = true, }; @@ -658,6 +700,8 @@ static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync, + .runtime_resume = qcom_adreno_smmu_runtime_resume, + .runtime_suspend = qcom_adreno_smmu_runtime_suspend, .context_fault_needs_threaded_irq = true, }; @@ -667,11 +711,14 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, const struct device_node *np = smmu->dev->of_node; const struct arm_smmu_impl *impl; struct qcom_smmu *qsmmu; + bool is_adreno_smmu; + int ret; if (!data) return ERR_PTR(-EINVAL); - if (np && of_device_is_compatible(np, "qcom,adreno-smmu")) + is_adreno_smmu = np && of_device_is_compatible(np, "qcom,adreno-smmu"); + if (is_adreno_smmu) impl = data->adreno_impl; else impl = data->impl; @@ -691,6 +738,12 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->data = data; + if (is_adreno_smmu) { + ret = qcom_adreno_smmu_icc_init(&qsmmu->smmu); + if (ret) + return ERR_PTR(ret); + } + return &qsmmu->smmu; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index 8addd453f5f1..6835b40339ce 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -6,12 +6,15 @@ #ifndef _ARM_SMMU_QCOM_H #define _ARM_SMMU_QCOM_H +#include + struct qcom_smmu { struct arm_smmu_device smmu; const struct qcom_smmu_match_data *data; bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; + struct icc_path *icc_path; }; enum qcom_smmu_impl_reg_offset { diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 0bd21d206eb3..a27804e15738 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -2189,6 +2189,14 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (err) return err; + if (smmu->impl && smmu->impl->runtime_resume) { + err = smmu->impl->runtime_resume(smmu); + if (err) { + clk_bulk_disable_unprepare(smmu->num_clks, smmu->clks); + return err; + } + } + err = arm_smmu_device_cfg_probe(smmu); if (err) return err; @@ -2273,8 +2281,11 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev) if (pm_runtime_enabled(smmu->dev)) pm_runtime_force_suspend(smmu->dev); - else + else { clk_bulk_disable(smmu->num_clks, smmu->clks); + if (smmu->impl && smmu->impl->runtime_suspend) + smmu->impl->runtime_suspend(smmu); + } clk_bulk_unprepare(smmu->num_clks, smmu->clks); } @@ -2294,9 +2305,18 @@ static int __maybe_unused arm_smmu_runtime_resume(struct device *dev) struct arm_smmu_device *smmu = dev_get_drvdata(dev); int ret; + if (smmu->impl && smmu->impl->runtime_resume) { + ret = smmu->impl->runtime_resume(smmu); + if (ret) + return ret; + } + ret = clk_bulk_enable(smmu->num_clks, smmu->clks); - if (ret) + if (ret) { + if (smmu->impl && smmu->impl->runtime_suspend) + smmu->impl->runtime_suspend(smmu); return ret; + } arm_smmu_device_reset(smmu); @@ -2309,6 +2329,9 @@ static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) clk_bulk_disable(smmu->num_clks, smmu->clks); + if (smmu->impl && smmu->impl->runtime_suspend) + return smmu->impl->runtime_suspend(smmu); + return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 26d2e33cd328..ed08f86cf99d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -455,6 +455,8 @@ struct arm_smmu_impl { void (*write_s2cr)(struct arm_smmu_device *smmu, int idx); void (*write_sctlr)(struct arm_smmu_device *smmu, int idx, u32 reg); void (*probe_finalize)(struct arm_smmu_device *smmu, struct device *dev); + int (*runtime_resume)(struct arm_smmu_device *smmu); + int (*runtime_suspend)(struct arm_smmu_device *smmu); }; #define INVALID_SMENDX -1 -- 2.34.1