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Mon, 06 Jul 2026 07:14:16 -0700 (PDT) Received: from hu-mchunara-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38127ae5b06sm5118416a91.3.2026.07.06.07.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2026 07:14:15 -0700 (PDT) From: Monish Chunara X-Google-Original-From: Monish Chunara To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Nitin Rawat , Pradeep Pragallapati , Komal Bajaj , Sachin Rathore , Monish Chunara , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov Subject: [PATCH V3 3/4] arm64: dts: qcom: Add SD Card support for Glymur SoC Date: Mon, 6 Jul 2026 19:43:45 +0530 Message-Id: <20260706141346.4180348-4-mchunara@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260706141346.4180348-1-mchunara@oss.qualcomm.com> References: <20260706141346.4180348-1-mchunara@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDE0NSBTYWx0ZWRfX4YfvBVRH7ybB 24I249+U0G+tS/mrTTI213818eHa3taLorCwshUr92gktX/KuHMvbvOitv5ufzPZg7R8t28fe3l pOQ2F+gNtbJpm4RKX9IR4vwz4e6Qtjc= X-Proofpoint-GUID: RvpyLWNq7mjY-zZTCJIygBvPj3k2vX6e X-Authority-Analysis: v=2.4 cv=C6zZDwP+ c=1 sm=1 tr=0 ts=6a4bb839 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=9wC1NwHXjCwt_iaUHW8A:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: RvpyLWNq7mjY-zZTCJIygBvPj3k2vX6e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDE0NSBTYWx0ZWRfX0KmRv3Rih38X /APnry/H8oAcSt8DwPPe4j7gm2S1dEGd3/Dc8GupNX02KxjXTzH8CkOdlPPOEkVd0jXrjkk9GL/ Z0C2P9gqXMhLjfoVd7nhCB1x3KZcdSftc+dnaxxQVnI2zUgPvyDbvXArfvHpljtJaNtKZZxySgs I6svKxUb6GL3O1V1wI2s15TBPgbNesj73OqKvsgyZG1QLhMNvEuQE/ML3s+5ye2bQOo+vWJQHXf KZBefGoeIumB2MK7iXadnX6CNJJXuBIpevLJUh+7eobDVsbczCbCPoXb+dNPq7Vo08/EI27TrGe ysAg3s/mxWPJBc1z+Pubvewsu8oMz8kZKgH78kr7TmNirLDMFUFVuTWiasBgx6YuP9j70sj11W2 CQ99m+MbOv01w/NhfeOdhNNPeJ0dj8PBDQxWf4ovilSGB6GbRvKFuWofGlxMQEF76IFtEHv7KZ3 8JbiwutCg9DtQC+xTtw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_01,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060145 From: Monish Chunara Add support for SD card on Glymur SoC and enable the required pinctrl configurations. Co-developed-by: Sachin Rathore Signed-off-by: Sachin Rathore Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Monish Chunara --- arch/arm64/boot/dts/qcom/glymur.dtsi | 91 ++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index e1c9cfee1ddb..ad70c9670008 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4149,6 +4149,58 @@ lpass_ag_noc: interconnect@7e40000 { #interconnect-cells = <2>; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5"; + + reg = <0x0 0x08804000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + iommus = <&apps_smmu 0xd00 0x0>; + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + interconnects = <&aggre3_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + bus-width = <4>; + dma-coherent; + + resets = <&gcc GCC_SDCC2_BCR>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb_2_hsphy: phy@88e0000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -5936,6 +5988,45 @@ rx-pins { bias-disable; }; }; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; stm: stm@10002000 { -- 2.34.1