From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 085AC37A849 for ; Tue, 7 Jul 2026 09:22:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783416137; cv=none; b=t2KEaisUnZ7QV+IZ/hlPPebfAhOa0GufxdNKko0TQsnNxRdKaX3/bcFAD6Yg9q/3fBZCLEsR0szs2H3DmhDRmWFRJ17y7N2P/nz4U0COR1kyRtx3kKxSfcUKwOjzg1X4ypcvyI6GZ7ou2Wzz03HfqvKDcJ9zOBZN/T3eI3DYYs8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783416137; c=relaxed/simple; bh=D0sOlcjYWpVb4KW1woV12cTMyxTCQuYuBDIGFgr0z8Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KfoIRy2x1L1wMqt7dK+MbHCg01crGzt9P62VG2fEaZLHHTw8lvzJvffLp1FSUu7Xdy41LD2DeQVyqof9W9VvACI8qtJ2+Dq9wL4rMmQ4MtCilbR1WAKZZVe93u0nDuyDOD9CDeI8S0nQ2g9goqpIQsDpYjCPoU2NBuXJopEjR9U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Eaw0Xrkr; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=V6Ag0dal; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Eaw0Xrkr"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="V6Ag0dal" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6678Dj4g3138631 for ; Tue, 7 Jul 2026 09:22:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2InzJMBKoHl7JVhFO+rX+aFvUpIrUtHbvFpQlkWzNFk=; b=Eaw0XrkrHQM1IAz7 pTYq7uvQ0D+ytlDUJz3ndv+Pau+PujnS6wZWjkQ+T1ZU1EbzzYAhhIb9f1mqK3le oRNzAvPOAG6XrV/AzRZUxQ0Mudjx1B58wINdCfj/XYETN/K4gAHId4EIscc1bXP3 OX7VyGNkQQDR/g9Qj/QP11q6TrGJkR31H3fC3grgWJL+imgUTAT89BdjRZLrk5Q3 yg8ZonPk+zM8tLhxgUFvUmfYqoN8K/nphVdSQuh8VzMd8K/mRdxOtKzSAGbDpDFy 7LilAdO4GFrAb4DFcyB4WGhQtb8/YacVBaWk1G+QHl8wmUMgZvhxY4W51VnPKc6n BpxThw== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f8t1597m9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 07 Jul 2026 09:22:13 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-c88ad1558f4so6691689a12.2 for ; Tue, 07 Jul 2026 02:22:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1783416133; x=1784020933; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2InzJMBKoHl7JVhFO+rX+aFvUpIrUtHbvFpQlkWzNFk=; b=V6Ag0dal0jtOskiiSUlLiTGgMeouQiNhFmL+t0U/5qstFPjchvO775N5VbrFPslqOS jhGc9OeYDu4tKkJ03ZQPTKfMtJdigCt9Qz7eQo1MckKVvPOEryfvRuDl0ujl1AEpTKSY 58U4Bf/jy0wFE9jtyTqUckoJ1wvR30lW4A+QNP3vbHBd0SGnnvsraHZPL79Sp9ZL5LS6 a6qbmAINxV1MBTepALX6biKCJ5SlYZXiCiBq7bH8v9K1M2mJbVsyS/306+oIcWMo59rS aX1bJevgLixNlJYrb+r4nhiBcNvzLapPQ3+KfNFEtIm4jsr0cJOv3PfWQgpmSoOnYrHL K7BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783416133; x=1784020933; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2InzJMBKoHl7JVhFO+rX+aFvUpIrUtHbvFpQlkWzNFk=; b=lK9Zs+aDjqQm+IW0CKVNO2Uj94vDV4zQIxzlrNFR0QfkaPGYt5BZCYO0nKnf+MtI5k B16AGlJJMpFRXRlji62Gg9ypRksfKoIqzzXYetoejtER0f34vHWF6/JoLL5z8Q1eB7Gi w2JdlolTOCcn5VThEVLyy3Jxw80c7STJYfAJo627InL3jYzBMBgaeBsAxSfUGa5pfcJL UMTzwhPGxLZBnWHSSYd+HqQI/rFo8R/l1GFPP3jJpasAQWmSHc56zrS52kxLqJWmaJqo GdkRRCVoEiYxr5b299nDK4HJFF3fHcfCxlyoH1lVYYf6b7p99O7hqvBFTw+nqfEdB47S lWUQ== X-Forwarded-Encrypted: i=1; AHgh+RpfCghWIrJ21lYi0KCuGZkEF+JQQcKEvhBUBbkr4Ggg8E3PfgWBcy1tV45YE8ek6WJ7zYtylgDh5D0tcRk=@vger.kernel.org X-Gm-Message-State: AOJu0Yyi52rgZexfgA6oqlIXO+s2AQISHjkEildN6Tl3M0qaumPFWlEN XATrN5RIZ93LEipMm1R3caW0+0lQSGtgMvdNvmRfSd0P6UeVPwDxsZQpyFnHp2oaJoQ30hlmUT6 qr2RYCwCw/PMOjPH4Nz+eAQBqybQPCVMBDzpSOwhfPven2ov8vJBB8L3ez95KLowU8n8= X-Gm-Gg: AfdE7cndV6VO0Yf5R8V7PRNbW+6N0Hte1KNj6stOs9fpWdV/KI2xyM0vmwlSEHszNQP 0g0wph6VeAnlnOkyrOuO662dnt0QngZP/vldWy27kyIObt/+Ub+ZttQHnG/Mp4+5BcFmEOToJCG BMCN7drrDSeyrBtmcKHaWiczEsJQo0f3CKnP9ZVWmOk0wKL9yWpHyMkO5BiBVi/6QJs5dDazRFS oiVhYmYR1T8DgFm80clCrlbEuImSHVqLHcuKToL+PRoY2AwglHLGvlqf7rSx+CMuOf5elcgjzPE lnoYUk+LXe7d6UNmJn67sqSP0pRk8IfZnDprpgmmMjCcsz79GwBdwoofF9KmjrPI77WDdt9utTD r0M/QndDDOml2t0/QYWujtt7WtVFxwErCrlT+/LA= X-Received: by 2002:a05:6a21:1b85:b0:3bf:d487:4b42 with SMTP id adf61e73a8af0-3c08ef051a0mr5861192637.35.1783416132721; Tue, 07 Jul 2026 02:22:12 -0700 (PDT) X-Received: by 2002:a05:6a21:1b85:b0:3bf:d487:4b42 with SMTP id adf61e73a8af0-3c08ef051a0mr5861153637.35.1783416132179; Tue, 07 Jul 2026 02:22:12 -0700 (PDT) Received: from hu-mkshah-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ca5afdb7534sm658864a12.12.2026.07.07.02.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2026 02:22:11 -0700 (PDT) From: Maulik Shah Date: Tue, 07 Jul 2026 14:51:35 +0530 Subject: [PATCH v4 3/7] irqchip/qcom-pdc: Differentiate between direct SPI and GPIO as SPI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260707-hamoa_pdc_v3-v4-3-dfd1f4a3ae89@oss.qualcomm.com> References: <20260707-hamoa_pdc_v3-v4-0-dfd1f4a3ae89@oss.qualcomm.com> In-Reply-To: <20260707-hamoa_pdc_v3-v4-0-dfd1f4a3ae89@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij , Bartosz Golaszewski Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad , Maulik Shah X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783416112; l=4238; i=maulik.shah@oss.qualcomm.com; s=20240109; h=from:subject:message-id; bh=D0sOlcjYWpVb4KW1woV12cTMyxTCQuYuBDIGFgr0z8Q=; b=1pX9sNDj1Pci8+qfn41oZdkQXZRGfcZizRvaXxJLxdF+NyAL7KnT9upuPoV1wdOnWugMNhjlC 7SUuYKr16nMAnatdA8xm4avp5jkcwU14z6qcfSqQXA5nWw/lqlw7WFo X-Developer-Key: i=maulik.shah@oss.qualcomm.com; a=ed25519; pk=bd9h5FIIliUddIk8p3BlQWBlzKEQ/YW5V+fe759hTWQ= X-Proofpoint-GUID: 4eNNOtlmEJpe1TKcNY8BgMqD17Lgj6aE X-Authority-Analysis: v=2.4 cv=HstG3UTS c=1 sm=1 tr=0 ts=6a4cc545 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=l_4bIUA77Uey-hlc_bsA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: 4eNNOtlmEJpe1TKcNY8BgMqD17Lgj6aE X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA3MDA5MCBTYWx0ZWRfX0CL9F7euu7Rb mi3zugf1qFlLbbAM5SCOdli+35NdcWsGA7tJG9yQvLGL6ZO2Ra6r9tgI95WM/w2fEIfFEADAyRl a4vd3mSPs97c+LJn/V3hj5jE3W1+v1k= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA3MDA5MCBTYWx0ZWRfXyUT+z5hxkfk3 bnK6fuZRVsNASbzro1u7bKq+o1kEO88WmzlFmO3wTZgKtiYlqbbC31iAjZ2CT7Vevp12O9vaKMe goW/S5t//XdPfDSr1zq32/FJ0b2ygB87J3+eDTdibRfqWSCMrF55CjCZPvJ3SBYukuIek3GQndq YKQQQma3w8f7RxpiK46oVjIZhWaqNHqvKTh829ej6kTGbykr57Ja05SpXyCP6D0HheIYbMcBm4b P/7TgHgp4U2VwIheK+hTtHW03yZyNtBb0VGjSE1TUIdYod9TgtzS6zfPVUVycmhVNPwCHAhHrRh Zs/2eWAJKvrdQkrvofwmjXI5uIxVmLI16i2/Z3/ZKwp/y0Kq1vCKskSSdw5gIRVDvS6MUvgneNY Vll8ceWVXBGygyZM6jwtVmoWCgaCQzLiy861fknpEUZyUlEDhdUwK8z45kXW482BT0Io8W28PZc V1r+YBBhP8DMWxRTJmg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_02,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607070090 Before commit 4dc70713dc24 ("irqchip/qcom-pdc: Kill non-wakeup irqdomain") there were separate domains for direct SPIs and GPIOs used as SPIs. Separate domains can be useful in case the irqchip wants to differentiate both of them. Since the commit unified both the domains there is no way to differentiate. In preparation to add the second level interrupt controller support where GPIO interrupts get latched at PDC (but not direct SPIs) there is a need to differentiate between SPIs and GPIOs as SPIs. Reverting above commit does not seem a good option which leads to waste of resources. PDC HW have the IRQ_PARAM register telling number of direct SPIs and number of GPIOs as SPIs. Further PDC allocates direct SPIs at the beginning and all GPIOs as SPIs are allocated at the end. This information can be used in driver to differentiate them. Add the support to read this register and keep this information in struct pdc_desc. Later change utilizes same. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 764f7965cfb8..53a477aa9765 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -61,6 +61,11 @@ * | | [4] GPIO_STATUS| [4] GPIO_MASK | * | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE | * | [0:2] Type | [0:2] Type | [0:2] Type | + * |---------------------------------------------------------------| + * | IRQ_PARAM | IRQ_PARAM | IRQ_PARAM | + * | | | + * | [15:8] NUM_GPIO | [15:8] NUM_GPIO | [15:8] NUM_GPIO | + * | [7:0] NUM_SPI | [7:0] NUM_SPI | [7:0] NUM_SPI | * +---------------------------------------------------------------+ */ @@ -69,10 +74,12 @@ * * @irq_en_reg: IRQ_ENABLE_BANK register location * @irq_cfg_reg: IRQ_CFG register location + * @irq_param_reg: IRQ_PARAM register location */ struct pdc_regs { u32 irq_en_reg; u32 irq_cfg_reg; + u32 irq_param_reg; }; /** @@ -92,6 +99,7 @@ struct pdc_irq_cfg { * @base: PDC base register for DRV2 / HLOS * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. * @version: PDC version + * @num_spis: Total number of direct SPI interrupts * @region: PDC interrupt continuous range * @region_cnt: Total PDC ranges * @x1e_quirk: x1e H/W Bug handling @@ -104,6 +112,7 @@ struct pdc_desc { void __iomem *base; void __iomem *prev_base; u32 version; + u32 num_spis; struct pdc_pin_region *region; int region_cnt; @@ -120,6 +129,7 @@ struct pdc_desc { static const struct pdc_regs pdc_v3_2 = { .irq_cfg_reg = 0x110, + .irq_param_reg = 0x100c, }; static const struct pdc_irq_cfg pdc_cfg_v3_2 = { @@ -130,6 +140,7 @@ static const struct pdc_irq_cfg pdc_cfg_v3_2 = { static const struct pdc_regs pdc_v3_0 = { .irq_en_reg = 0x10, .irq_cfg_reg = 0x110, + .irq_param_reg = 0x100c, }; static const struct pdc_irq_cfg pdc_cfg_v3_0 = { @@ -139,6 +150,7 @@ static const struct pdc_irq_cfg pdc_cfg_v3_0 = { static const struct pdc_regs pdc_v2_7 = { .irq_en_reg = 0x10, .irq_cfg_reg = 0x110, + .irq_param_reg = 0x100c, }; static const struct pdc_irq_cfg pdc_cfg_v2_7 = { @@ -445,6 +457,7 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare struct device *dev = &pdev->dev; resource_size_t res_size; struct resource res; + u32 irq_param; int ret; /* compat with old sm8150 DT which had very small region for PDC */ @@ -501,6 +514,9 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare pdc->x1e_quirk = true; } + irq_param = pdc_reg_read(pdc->regs->irq_param_reg, 0); + pdc->num_spis = FIELD_GET(GENMASK(7, 0), irq_param); + parent_domain = irq_find_host(parent); if (!parent_domain) { pr_err("%pOF: unable to find PDC's parent domain\n", node); -- 2.43.0