From: Charlie Jenkins <thecharlesjenkins@gmail.com>
To: "Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Nam Cao" <namcao@linutronix.de>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atish.patra@linux.dev>,
"Conor Dooley" <conor@kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Shuah Khan" <shuah@kernel.org>,
"Radim Krčmář" <radim.krcmar@oss.qualcomm.com>,
"Jesse Taube" <jtaubepe@redhat.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: [PATCH v3 03/17] riscv: kgdb: Use generated instruction headers
Date: Tue, 07 Jul 2026 20:34:26 -0700 [thread overview]
Message-ID: <20260707-riscv_insn_table-v3-3-3f8e5f75ba97@gmail.com> (raw)
In-Reply-To: <20260707-riscv_insn_table-v3-0-3f8e5f75ba97@gmail.com>
Migrate the code that is decoding instructions for the use of kgdb
single stepping to use the generated instruction headers instead of the
hand-written instruction functions.
Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
---
I tested this again by comparing the original get_step_address()
function with this new version and input all possible 32 bit numbers and
checked that the next_addr was the same in every case.
This is the code I used:
void check_step()
{
for (unsigned long opcode = 0; opcode < ((1ULL << 32) - 1); opcode++) {
unsigned long next_addr, next_addr2;
get_step_address(opcode, &next_addr);
get_step_address2(opcode, &next_addr2);
if (next_addr != next_addr2) {
printf("opcode: %lu -> %lu != %lu\n", opcode, next_addr, next_addr2);
}
}
}
---
arch/riscv/include/asm/insn.h | 21 +++++++++
arch/riscv/kernel/kgdb.c | 102 ++++++++++++++++--------------------------
2 files changed, 60 insertions(+), 63 deletions(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index d0e137f9bcd7..b92c71896c00 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -514,4 +514,25 @@ static __always_inline bool riscv_insn_is_branch(u32 code)
#define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
+static inline unsigned long riscv_insn_reg_get_val(unsigned long *regs, u32 index)
+{
+ /* register 0 is always 0 and not stored in the register struct */
+ return index ? *(regs + index) : 0;
+}
+
+#define riscv_insn_branch(_insn, regs_ptr, _opcode, _pc, _comparison, type) \
+ ({ \
+ unsigned long _ret; \
+ if ((type)riscv_insn_reg_get_val( \
+ regs_ptr, \
+ riscv_insn_##_insn##_extract_xs1(_opcode)) \
+ _comparison(type) riscv_insn_reg_get_val( \
+ regs_ptr, \
+ riscv_insn_##_insn##_extract_xs2(_opcode))) \
+ _ret = _pc + riscv_insn_##_insn##_extract_imm(_opcode); \
+ else \
+ _ret = _pc + 4; \
+ _ret; \
+ })
+
#endif /* _ASM_RISCV_INSN_H */
diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c
index 0bf629204c76..fcf7cda3cc33 100644
--- a/arch/riscv/kernel/kgdb.c
+++ b/arch/riscv/kernel/kgdb.c
@@ -23,97 +23,73 @@ enum {
static unsigned long stepped_address;
static unsigned int stepped_opcode;
-static int decode_register_index(unsigned long opcode, int offset)
-{
- return (opcode >> offset) & 0x1F;
-}
-
-static int decode_register_index_short(unsigned long opcode, int offset)
-{
- return ((opcode >> offset) & 0x7) + 8;
-}
-
-/* Calculate the new address for after a step */
static int get_step_address(struct pt_regs *regs, unsigned long *next_addr)
{
unsigned long pc = regs->epc;
unsigned long *regs_ptr = (unsigned long *)regs;
- unsigned int rs1_num, rs2_num;
+ unsigned int rs1_num;
int op_code;
if (get_kernel_nofault(op_code, (void *)pc))
return -EINVAL;
+
if ((op_code & __INSN_LENGTH_MASK) != __INSN_LENGTH_GE_32) {
- if (riscv_insn_is_c_jalr(op_code) ||
- riscv_insn_is_c_jr(op_code)) {
- rs1_num = decode_register_index(op_code, RVC_C2_RS1_OPOFF);
- *next_addr = regs_ptr[rs1_num];
- } else if (riscv_insn_is_c_j(op_code) ||
- riscv_insn_is_c_jal(op_code)) {
- *next_addr = RVC_EXTRACT_JTYPE_IMM(op_code) + pc;
+ if (riscv_insn_is_c_jalr(op_code)) {
+ *next_addr = regs_ptr[riscv_insn_c_jalr_extract_xs1(op_code)];
+ } else if (riscv_insn_is_c_jr(op_code)) {
+ *next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(op_code)];
+ } else if (riscv_insn_is_c_j(op_code)) {
+ *next_addr = riscv_insn_c_j_extract_imm(op_code) + pc;
+ } else if (riscv_insn_is_c_jal(op_code)) {
+ *next_addr = riscv_insn_c_jal_extract_imm(op_code) + pc;
} else if (riscv_insn_is_c_beqz(op_code)) {
- rs1_num = decode_register_index_short(op_code,
- RVC_C1_RS1_OPOFF);
- if (!rs1_num || regs_ptr[rs1_num] == 0)
- *next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc;
+ rs1_num = riscv_insn_c_beqz_extract_xs1(op_code);
+ if (regs_ptr[8 + rs1_num] == 0)
+ *next_addr = riscv_insn_c_beqz_extract_imm(op_code) + pc;
else
*next_addr = pc + 2;
} else if (riscv_insn_is_c_bnez(op_code)) {
- rs1_num =
- decode_register_index_short(op_code, RVC_C1_RS1_OPOFF);
- if (rs1_num && regs_ptr[rs1_num] != 0)
- *next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc;
+ rs1_num = riscv_insn_c_bnez_extract_xs1(op_code);
+ if (regs_ptr[8 + rs1_num] != 0)
+ *next_addr = riscv_insn_c_bnez_extract_imm(op_code) + pc;
else
*next_addr = pc + 2;
} else {
*next_addr = pc + 2;
}
} else {
- if ((op_code & __INSN_OPCODE_MASK) == __INSN_BRANCH_OPCODE) {
- bool result = false;
- long imm = RV_EXTRACT_BTYPE_IMM(op_code);
- unsigned long rs1_val = 0, rs2_val = 0;
-
- rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
- rs2_num = decode_register_index(op_code, RVG_RS2_OPOFF);
- if (rs1_num)
- rs1_val = regs_ptr[rs1_num];
- if (rs2_num)
- rs2_val = regs_ptr[rs2_num];
-
- if (riscv_insn_is_beq(op_code))
- result = (rs1_val == rs2_val) ? true : false;
- else if (riscv_insn_is_bne(op_code))
- result = (rs1_val != rs2_val) ? true : false;
- else if (riscv_insn_is_blt(op_code))
- result =
- ((long)rs1_val <
- (long)rs2_val) ? true : false;
- else if (riscv_insn_is_bge(op_code))
- result =
- ((long)rs1_val >=
- (long)rs2_val) ? true : false;
- else if (riscv_insn_is_bltu(op_code))
- result = (rs1_val < rs2_val) ? true : false;
- else if (riscv_insn_is_bgeu(op_code))
- result = (rs1_val >= rs2_val) ? true : false;
- if (result)
- *next_addr = imm + pc;
- else
- *next_addr = pc + 4;
+ if (riscv_insn_is_beq(op_code)) {
+ *next_addr = riscv_insn_branch(beq, regs_ptr, op_code,
+ pc, ==, unsigned long);
+ } else if (riscv_insn_is_bne(op_code)) {
+ *next_addr = riscv_insn_branch(bne, regs_ptr, op_code,
+ pc, !=, unsigned long);
+ } else if (riscv_insn_is_blt(op_code)) {
+ *next_addr = riscv_insn_branch(blt, regs_ptr, op_code,
+ pc, <, long);
+ } else if (riscv_insn_is_bge(op_code)) {
+ *next_addr = riscv_insn_branch(bge, regs_ptr, op_code,
+ pc, >=, long);
+ } else if (riscv_insn_is_bltu(op_code)) {
+ *next_addr = riscv_insn_branch(bltu, regs_ptr, op_code,
+ pc, <, unsigned long);
+ } else if (riscv_insn_is_bgeu(op_code)) {
+ *next_addr = riscv_insn_branch(bgeu, regs_ptr, op_code,
+ pc, >=, unsigned long);
} else if (riscv_insn_is_jal(op_code)) {
- *next_addr = RV_EXTRACT_JTYPE_IMM(op_code) + pc;
+ *next_addr = riscv_insn_jal_extract_imm(op_code) + pc;
} else if (riscv_insn_is_jalr(op_code)) {
- rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
+ rs1_num = riscv_insn_jalr_extract_xs1(op_code);
if (rs1_num)
- *next_addr = ((unsigned long *)regs)[rs1_num];
- *next_addr += RV_EXTRACT_ITYPE_IMM(op_code);
+ *next_addr = regs_ptr[rs1_num];
+ *next_addr += riscv_insn_jalr_extract_imm(op_code);
} else if (riscv_insn_is_sret(op_code)) {
*next_addr = pc;
} else {
*next_addr = pc + 4;
}
}
+
return 0;
}
--
2.54.0
next prev parent reply other threads:[~2026-07-08 3:36 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 3:34 [PATCH v3 00/17] riscv: Generate riscv instruction functions Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 01/17] riscv: Introduce instruction table generation Charlie Jenkins
2026-08-05 11:32 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 02/17] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins
2026-08-06 6:50 ` Nam Cao
2026-07-08 3:34 ` Charlie Jenkins [this message]
2026-08-06 7:09 ` [PATCH v3 03/17] riscv: kgdb: Use generated instruction headers Nam Cao
2026-07-08 3:34 ` [PATCH v3 04/17] riscv: Add kprobes instruction simulation KUnit Charlie Jenkins
2026-08-06 8:23 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 05/17] riscv: kprobes: Use generated instruction headers Charlie Jenkins
2026-08-06 8:30 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 06/17] riscv: cfi: " Charlie Jenkins
2026-08-06 8:30 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 07/17] riscv: Maintain epc on misaligned emulation error Charlie Jenkins
2026-08-06 8:38 ` Nam Cao
2026-08-06 16:36 ` Damien Le Moal
2026-07-08 3:34 ` [PATCH v3 08/17] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins
2026-08-06 14:45 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 09/17] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins
2026-08-06 15:04 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 10/17] KVM: device: Add test device Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 11/17] KVM: riscv: selftests: Add mmio test Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 12/17] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 13/17] riscv: kvm: Add emulated test csr Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 14/17] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 15/17] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 16/17] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 17/17] riscv: Remove unused instruction headers Charlie Jenkins
2026-07-09 6:26 ` [syzbot ci] Re: riscv: Generate riscv instruction functions syzbot ci
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