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Enable PCIe1 and its QMP PHY nodes. TC9563 uses I2C (at address 0x77 on I2C4) for its management interface. Override the base iommu-map with the expanded set covering all the switch's downstream ports (0x1400-0x1408 SID range). The TC9563 RESX# and PERST# are OR-ed internally to assert reset on the switch. Use TC9563 RESX# pin via a TLMM GPIO and skip wiring PERST# from the PCIe controller. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 112 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/eliza.dtsi | 1 + 2 files changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi index 6d76715ccffb..e099b7c8c371 100644 --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi @@ -12,6 +12,26 @@ chosen { stdout-path = "serial0:115200n8"; }; + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + vreg_pcie_m_3p3: regulator-3p3 { compatible = "regulator-fixed"; @@ -99,6 +119,98 @@ pcieport0_ep: endpoint { }; }; +&pcie1 { + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>, + <0x208 &apps_smmu 0x1402 0x1>, + <0x210 &apps_smmu 0x1403 0x1>, + <0x218 &apps_smmu 0x1404 0x1>, + <0x300 &apps_smmu 0x1405 0x1>, + <0x400 &apps_smmu 0x1406 0x1>, + <0x500 &apps_smmu 0x1407 0x1>, + <0x501 &apps_smmu 0x1408 0x1>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l1k>; + vdda-pll-supply = <&vreg_l3k>; + + status = "okay"; +}; + +&pcie1port0 { + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + tc9563: pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c4 0x77>; + + resx-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &uart13 { compatible = "qcom,geni-debug-uart"; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index cce65e18f979..363cabc5f55c 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -2102,6 +2102,7 @@ opp-16000000-3 { }; pcie1port0: pcie@0 { + compatible = "pciclass,0604"; device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; -- 2.34.1