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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NrsmrR5l2Dl9eCA9ciyGA644augFtxGMmeZnk/04CzZLkeTsY/wNI+YMZQREnV/JJaFX0afp/x0Jmz9o1ppRVDhVQNx0OWiL1/PNJO1LDXe+Fnouw7QI3dKx4Fvpueec0V9y6wx69M7zIlbYDMKuYuCUIsvbrYuG01To6GvWEFtWHxoi7wabbFom6BEgil1uOrEXz47CRsdqx2ucrivlv1cmyZlnIlIjRyHP4oM2e5rznNXHWuvfi3uoHfLs4y8mTWprSypJci+as3sSUg8stL0y/9WPl+ZjKLxmvSGKE1yDOUGLkbJDND2qj5VW3EKWfZKAqlpjftCL3d83AJJfi60OrmGkovrxC1dj4hN6hkVwruKOLnicYoKRy6QwcJvNUFQ36QQuUKwMCTGs2EMI7m/z02aDGYxnTR0/miHL7Zk93B1mReYDqiHxQ4iiHiCd X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2026 01:56:59.2733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c82a042-5d33-4223-919a-08dedc943285 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7229 Notes: * This series depends on the "[PATCH v3 00/22] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support" (https://lore.kernel.org/linux-iommu/20260629153535.15775-1-suravee.suthikulpanit@amd.com/) * Previously, this series was part of the AMD HW vIOMMU series, and now is being split into its own series to make it easier to review. Overview: AMD HW-accelerated Virtualized IOMMU (vIOMMU) guests own command, event, and PPR queues in guest physical address space. The existing iommufd HW queue path pins host pages and passes a physical address to the driver via hw_queue_init_phys(). vIOMMU hardware instead consumes guest queue GPAs supplied by userspace through IOMMU_HW_QUEUE_ALLOC. This series adds a guest-address initialization path in the iommufd core and wires AMD vIOMMU VFCTRL programming for command, event, and PPR queues. Patch 1 factors HW queue allocation into _iommufd_hw_queue_init() and introduces hw_queue_init in iommufd_viommu_ops. Drivers that implement hw_queue_init receive the queue GPA in hw_queue->base_addr without the core pinning host backing pages. Patch 2 extends the IOMMU_HW_QUEUE_ALLOC UAPI with AMD queue types and per-queue enable flags, stores flags on iommufd_hw_queue, and programs guest command, event, and PPR control registers in VFCTRL during _amd_viommu_hw_queue_init(). * In this version, the CommandBuf, EventLog, and PPRLog are expected to be allocated when the corresponding enable bits in the guest IOMMU Control MMIO register are set, which is different from the previous version where the HW queue is allocated when the buffers base-address/size are programmed. Thanks, Suravee Suravee Suthikulpanit (2): iommufd: add hw_queue_init for guest-address queue setup iommu/amd: add vIOMMU HW queue initialization drivers/iommu/amd/amd_iommu_types.h | 8 ++ drivers/iommu/amd/iommufd.c | 129 ++++++++++++++++++++++++++++ drivers/iommu/iommufd/viommu.c | 95 +++++++++++--------- include/linux/iommufd.h | 6 +- include/uapi/linux/iommufd.h | 31 ++++++- 5 files changed, 228 insertions(+), 41 deletions(-) -- 2.34.1