From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E73133067C for ; Thu, 9 Jul 2026 13:42:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783604542; cv=none; b=TQK8TFg3qsdDVD9xYaJAcQ6pxjeBHU6O6usbaKxVYuY9HNdzPTWNwZ1XkB8k0/EQbSPRrWILK7il9vQVTy+3VPqHVp6X82PR7L8+AWGOk5HBxLAmNN8wkMQTgjIDARRLgxHnpROPFQ2dDsnQdz/H/FozlZ2gYCPgohAsYV3Dvtc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783604542; c=relaxed/simple; bh=cPTXXI3mknLotK+Tb+V1ad85mR3WKey4eZTl/ep3O08=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c+YhYOEdg/HkrvcwKZgKVJ78fki/GiyTc0YR2A95Ix4veOoxrGnz4YS2YdrCxQrFHtJlUqX5A8GW06ILDGdueYIRVTRZIFebCBAgChTSMb8O9ysZQYPNW8chZ1mjv93c5uhQVmo4vdLdrSMYYdPb1A7e9+xWJGpRs+zKZ1bjJSE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=AHNlYQTf; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=G+tpaNob; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="AHNlYQTf"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="G+tpaNob" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 669BNBIh1575375 for ; Thu, 9 Jul 2026 13:42:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ww3O+xZWHTL3y5Bq6dWUkA7w+aF9j0eNrHZL0WdKA3Y=; b=AHNlYQTfq+YLB02n jPF4hH6dtpFyQ0pqebLOr9aMd2/rv3WTrtBp5RsNTgITWPM/PhdklWZeya33yh4R u2Lj2CIijI0EOGQPeAvnyZwNIJJygsEXZX+kZn0UoqzR3mdlLXPfSVDu5RR9uAjt r2XJ4vgR83zfDZjTmN/zD6PlRXk1kWhTwa9iL+ezn/I86Mup3NjhMVW02xBbNV/w kfhSwA0GW0oZ4W9un9BdirUEvcyeKDUEwah3vu8xvjUWxf4Fn15No8f6MzAcFfzp jcPHyiUeoSAypdDCK5yejE3HCKth2tRooIC1Tm1iELuHmtiXRaTXN1xZoiuhfnb5 swR6iw== Received: from mail-vs1-f69.google.com (mail-vs1-f69.google.com [209.85.217.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f9sqwcfv9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 09 Jul 2026 13:42:20 +0000 (GMT) Received: by mail-vs1-f69.google.com with SMTP id ada2fe7eead31-737d34a0dc8so998158137.1 for ; Thu, 09 Jul 2026 06:42:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1783604540; x=1784209340; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ww3O+xZWHTL3y5Bq6dWUkA7w+aF9j0eNrHZL0WdKA3Y=; b=G+tpaNobfOW0kpbNefOuaPPruKmX607ikt22ktBfmLP5Lb1jhGJMcuX2BHJhe25Ovk X+m0Uwbhp1tJfAFovqsZ7CWKSQ/Erq/kzbhfqOnVQE8DwOnXBiCaaEk6QpY5Qk8Iq7Mz sgRjg2pTXgCE+dDJ3DA6DA1vrDmnlMZfXMpUTdRUerIIkt47w2ckFgSAv8Y4dA3MAzvk dQHVhOUCkbfJ9DPPwKS3jse/bDIsscUmdCukscJGxdJw1NVxkXDIt1UcZ77cyYkE2Lqi Jen09QAScNE9YgxB1wCZUZ/ltMisozcQY3/UGuFvVikgDqPXbxcZvfdt2ELVIPO/+szJ 0A1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783604540; x=1784209340; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ww3O+xZWHTL3y5Bq6dWUkA7w+aF9j0eNrHZL0WdKA3Y=; b=sMKbwWM+BtcemaKiVEQM8d0Kdf8kI8mxTgLcHDnQC3AbWsNIwXUTGhu0x4GhQogyjk qU1Eco7EumTvMHrokfw/ykLP+oLx+CLiUhz4C+Qaad0LO2gfg+/Jy11L1JaHyfwuyhHy Wxui8cLylxIENIsNpUNS5IJN/G0BDqmzoZhxFBoyEkQNRcq6tdjCMLRaiJtSL41jnUyC U5/FDPF+vTo2GV9DLFcJQkN8nuv0Cwmd0oHnEu9RO8v2LpHeMSA7AzBNsFhSDJxZfy9B umr1S7Caf9sMMfLCJAhXkm0AmtptaUPhZ6jzKS/8ygvq0NwgyATI0O58n0aNecDUsHmS b8/g== X-Forwarded-Encrypted: i=1; AHgh+RrE5U5LbE5OKzFmTh81RFA7PZp/sgQAJulj3dlmMEFxIetLpqZpZadwUaXnRZwLsVivxI9Qdff78agbhGk=@vger.kernel.org X-Gm-Message-State: AOJu0Yzag1e82CcXoCpRmA9FxGykKV6NnM8Sk+Y+IJZJajmeShiLd0fr OvcfNZG8vLFjojHWG+Hg28Z60MtLiPu+Ovcx4xVWfQr3FCHg9f3aKCvC/uSYDnwtZN0W93OYYcG q4/yzAXQKm7pWM0oT80r4Axnpfe8pgQ68fHUTGvJMusIOUldqADX5fNW/7llDDJCscxU= X-Gm-Gg: AfdE7ckU3faPR+uiiC5YMj1wkDJ+dvd6Tht8FkywhjGUDyYOCde4yE7zAPeJT/ZAmAz gp6wldiuwM6K+yBf5E+IZixu7YvCRXy7PMML8oYJABw/G3nfXAoI1Am8IV08lOTltyqQ7xb/Uog RpqemtFhhpFHwUZZJ4bhRCIx01/HeMp5arOSg0RVgRVJUKaAsT1qC4Pf8Ve3aCp6aSqY1uU2Fzt e5vrhaaEyIvRe1boZBRINRmmKPazhkUo8WZfeYzKnxp6TEgOGlXxKhpeLpc9f5Og7E1Voh5o75D i/dv3H9q99sC7Q8iyn6oseINLOWx5AdTnWOgbi6+6wDvdTQ4wURywSdXBLz6+ftXkBgGzn38Gvb +U3cvptjma6st+P2CpJdnBidl3PKm5WWpo3wuJ4P5ujMZzEC4ZzXdmAkx6oRK+MSj3iTky8QvLE qB0V4jiF0aggebe+9LaeTDEgLl X-Received: by 2002:a05:6102:f89:b0:744:cb59:d6e4 with SMTP id ada2fe7eead31-744dff883c1mr4748024137.22.1783604539575; Thu, 09 Jul 2026 06:42:19 -0700 (PDT) X-Received: by 2002:a05:6102:f89:b0:744:cb59:d6e4 with SMTP id ada2fe7eead31-744dff883c1mr4747988137.22.1783604538934; Thu, 09 Jul 2026 06:42:18 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-39c849186e1sm3345151fa.9.2026.07.09.06.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2026 06:42:17 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 09 Jul 2026 16:41:59 +0300 Subject: [PATCH v7 08/18] media: iris: Add platform data field for watchdog interrupt mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260709-iris-ar50lt-v7-8-76af9dd4d1f6@oss.qualcomm.com> References: <20260709-iris-ar50lt-v7-0-76af9dd4d1f6@oss.qualcomm.com> In-Reply-To: <20260709-iris-ar50lt-v7-0-76af9dd4d1f6@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6946; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=KKYwQvV6HfPLmLckhIvkwX1DNxqvTV0Ag1veh8Tp1rA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqT6UlQoHH4h8r9m/1xAdnLQWeWCfpk8+r97P5W nwLGSKwxeuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCak+lJQAKCRCLPIo+Aiko 1QRyB/9Ua/8ga0fyfM249+q4hk0FOEFtT0M7eL+v3TZEnjIckdjtWAzRpcU0gl9934IeBTIx5rx sItV4XomzcceIYM+FlWZh550XJsk+K8NklHQyIQ/kDfVDIXloXQ7duKWSee4Ck2C9Jm6RxxIH4A 84kV40saumdvDWT3RIFmrsSXQ+XqxfVPSe24DKOz+A4euIBzbYDFnLHA6exVckn72qI0xPJDCA1 Xzy+RJGGzuRgVxEZStvN9jll85Z6niwFhAOn98iUQtwosM2/aXDorMfJd4X32IGaf9hZXz3JWW/ uUAat0Nl7I22dmm8cb87Dd2bio6PCs9x2YJfvbvJpdUZQ4gw X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA5MDEzNCBTYWx0ZWRfX5ZomaZBdHMKX qS5/+gZh7AFe+Yq7GNTzqvodX/RekJpM5a+2PGxhmlvpJZkwxDycxOKztaEoORIBTT8YeQam+uQ 0mtGx4Qzskrjl6dYN6UjKwPMTDjW9IKO82Kc58Ff5Umsu+a2YfvAJise2dnCUauptxQ8sl7A4dv eFgdXdoJRA0QWcFobcE5AJexQ6C6IStv1d68SrKZDSe9aY4ND2MGrCom5Bco6p9J9i04qjMvwh6 6SreaIHVpGMqvhWxxAKDWrnEMde81dU/58ZV3SkjbXwwR8xdz3CFXDQ7ht8kycPnN2ZwdBLdcOA H+PFq6kpMdAw1A0VRlHuCwC5lkxtx93EZYWCI1GMbv4cJJ37ubGWYwhagoBev4sbdhv47EYQHZF hWRioZ6SNd+7C3bNHNskMq0YR7GEnB3y2EY5AfvMuDa2G3UITiSw/OonptnbxsowJnH6WzQv7O1 RSd7lkhLEqnB8JOhDeg== X-Proofpoint-GUID: tInhBNsNfV2AQVmikUTQ2J0n0L1HBbav X-Authority-Analysis: v=2.4 cv=fMIJG5ae c=1 sm=1 tr=0 ts=6a4fa53c cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=6vpm4igQ2ooD_hm6sYAA:9 a=QEXdDO2ut3YA:10 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-ORIG-GUID: tInhBNsNfV2AQVmikUTQ2J0n0L1HBbav X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA5MDEzNCBTYWx0ZWRfXyANs/pEnHQQi 6fDEik44++Lxy4KwlUg4EPSDKv4CDvn4RCvxZLGpqnLE8Q/AVr1XWHIUM/zhB3IFualVhn37z63 3TZZcofCZtxmEpK2tvTNjxGFvcAXTYg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-09_02,2026-07-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607090134 From: Dikshita Agarwal For AR50LT core, the value of WRAPPER_INTR_STATUS_A2HWD_BMASK differs from the currently supported VPUs. In preparation for adding AR50LT support in subsequent patches, introduce a platform data field, wd_intr_mask, to capture the watchdog interrupt bitmask per platform. Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 4 ++++ drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 7 +++++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 8 +++++--- drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 - 5 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 55a4fa356985..81fcb2854772 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -315,6 +315,7 @@ struct iris_platform_data { u32 tz_cp_config_data_size; u32 num_vpp_pipe; bool no_aon; + u32 wd_intr_mask; u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index ba91672df1bb..940daddbafcf 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -16,6 +16,8 @@ #include "iris_platform_sc7280.h" #include "iris_platform_sm8250.h" +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) + static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { .firmware_data = &iris_hfi_gen1_data, .get_vpu_buffer_size = iris_vpu_buf_size, @@ -94,6 +96,7 @@ const struct iris_platform_data sc7280_data = { .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe = 1, .no_aon = true, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count = 16, .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ @@ -124,6 +127,7 @@ const struct iris_platform_data sm8250_data = { .tz_cp_config_data = tz_cp_config_vpu2, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe = 4, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K, .max_core_mbps = ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index 7098b652c117..eeedde8fc9ce 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -18,6 +18,8 @@ #include "iris_platform_sm8750.h" #include "iris_platform_x1p42100.h" +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) + static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { .firmware_data = &iris_hfi_gen2_data, .get_vpu_buffer_size = iris_vpu_buf_size, @@ -113,6 +115,7 @@ const struct iris_platform_data qcs8300_data = { .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe = 2, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count = 16, .max_core_mbpf = ((4096 * 2176) / 256) * 4, .max_core_mbps = (((3840 * 2176) / 256) * 120), @@ -142,6 +145,7 @@ const struct iris_platform_data sm8550_data = { .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe = 4, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, @@ -179,6 +183,7 @@ const struct iris_platform_data sm8650_data = { .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe = 4, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, @@ -208,6 +213,7 @@ const struct iris_platform_data sm8750_data = { .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe = 4, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, @@ -243,6 +249,7 @@ const struct iris_platform_data x1p42100_data = { .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe = 1, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count = 16, .max_core_mbpf = NUM_MBS_8K * 2, .max_core_mbps = ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 375bcd923476..41498f94480e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -109,11 +109,11 @@ void iris_vpu_raise_interrupt(struct iris_core *core) void iris_vpu_clear_interrupt(struct iris_core *core) { + u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask; u32 intr_status, mask; intr_status = readl(core->reg_base + WRAPPER_INTR_STATUS); - mask = (WRAPPER_INTR_STATUS_A2H_BMSK | - WRAPPER_INTR_STATUS_A2HWD_BMSK | + mask = (WRAPPER_INTR_STATUS_A2H_BMSK | wd_intr_mask | CTRL_INIT_IDLE_MSG_BMSK); if (intr_status & mask) @@ -124,7 +124,9 @@ void iris_vpu_clear_interrupt(struct iris_core *core) int iris_vpu_watchdog(struct iris_core *core, u32 intr_status) { - if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK) { + u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask; + + if (intr_status & wd_intr_mask) { dev_err(core->dev, "received watchdog interrupt\n"); return -ETIME; } diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index 72168b9ffa73..4fffa094c52f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -41,7 +41,6 @@ #define MSK_CORE_POWER_ON BIT(1) #define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) #define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) #define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) -- 2.47.3