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The decode format list was however kept per-SoC in iris_platform_data::inst_iris_fmts, which is too coarse to express this - a per-SoC list cannot describe the two different format sets the same SoC exposes depending on which firmware it booted. Move the decode format list into struct iris_firmware_data, which is already selected per firmware generation, and drop the per-SoC inst_iris_fmts field. Each firmware data instance now carries the exact set of decode formats its generation supports, so the formats advertised to userspace always match the running firmware. No functional change: every SoC advertises the same decode formats as before. Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 12 ++++++++++++ drivers/media/platform/qcom/iris/iris_hfi_gen2.c | 21 +++++++++++++++++++++ .../media/platform/qcom/iris/iris_platform_common.h | 12 ++++++++++-- .../media/platform/qcom/iris/iris_platform_vpu2.c | 10 ---------- .../media/platform/qcom/iris/iris_platform_vpu3x.c | 17 ----------------- .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 8 -------- drivers/media/platform/qcom/iris/iris_vdec.c | 8 ++++---- 7 files changed, 47 insertions(+), 41 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c index 4f205757647a..8119c639ec24 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -419,6 +419,12 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = { BUF_SCRATCH_2, }; +static const u32 iris_hfi_gen1_dec_fmts[] = { + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_VP9, +}; + const struct iris_firmware_data iris_hfi_gen1_data = { .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, @@ -427,6 +433,9 @@ const struct iris_firmware_data iris_hfi_gen1_data = { .inst_fw_caps_enc = inst_fw_cap_sm8250_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc), + .dec_fmts = iris_hfi_gen1_dec_fmts, + .dec_fmts_size = ARRAY_SIZE(iris_hfi_gen1_dec_fmts), + .dec_input_config_params_default = sm8250_vdec_input_config_param_default, .dec_input_config_params_default_size = @@ -668,6 +677,9 @@ const struct iris_firmware_data iris_hfi_gen1_ar50lt_data = { .inst_fw_caps_enc = inst_fw_cap_gen1_ar50lt_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_gen1_ar50lt_enc), + .dec_fmts = iris_hfi_gen1_dec_fmts, + .dec_fmts_size = ARRAY_SIZE(iris_hfi_gen1_dec_fmts), + .dec_input_config_params_default = sm8250_vdec_input_config_param_default, .dec_input_config_params_default_size = diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c index 110b5630902f..6c1d562ab8c2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -1236,6 +1236,19 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { BUF_SCRATCH_2, }; +static const u32 iris_hfi_gen2_dec_fmts[] = { + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_VP9, + V4L2_PIX_FMT_AV1, +}; + +static const u32 iris_hfi_gen2_vpu2_dec_fmts[] = { + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_VP9, +}; + const struct iris_firmware_data iris_hfi_gen2_data = { .init_hfi_ops = iris_hfi_gen2_sys_ops_init, @@ -1246,6 +1259,9 @@ const struct iris_firmware_data iris_hfi_gen2_data = { .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), + .dec_fmts = iris_hfi_gen2_dec_fmts, + .dec_fmts_size = ARRAY_SIZE(iris_hfi_gen2_dec_fmts), + .dec_input_config_params_default = sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size = @@ -1317,6 +1333,9 @@ const struct iris_firmware_data iris_hfi_gen2_vpu2_data = { .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), + .dec_fmts = iris_hfi_gen2_vpu2_dec_fmts, + .dec_fmts_size = ARRAY_SIZE(iris_hfi_gen2_vpu2_dec_fmts), + .dec_input_config_params_default = sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size = @@ -1934,6 +1953,8 @@ const struct iris_firmware_data iris_hfi_gen2_ar50lt_data = { .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_dec), .inst_fw_caps_enc = inst_fw_cap_gen2_ar50lt_enc, .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_enc), + .dec_fmts = iris_hfi_gen2_vpu2_dec_fmts, + .dec_fmts_size = ARRAY_SIZE(iris_hfi_gen2_vpu2_dec_fmts), .dec_input_config_params_default = sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size = diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 9743573ab083..317ba48e6305 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -255,6 +255,16 @@ struct iris_firmware_data { const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; + /* + * List of coded formats supported by this firmware generation, used to + * advertise decode (bitstream) formats to userspace. This lives in the + * firmware data because a single SoC can boot either firmware + * generation, and some codecs (e.g. VP8, MPEG2, AV1) are only supported + * by one generation. + */ + const u32 *dec_fmts; + unsigned int dec_fmts_size; + const u32 *dec_input_config_params_default; unsigned int dec_input_config_params_default_size; const u32 *dec_input_config_params_hevc; @@ -317,8 +327,6 @@ struct iris_platform_data { const char * const *controller_rst_tbl; unsigned int controller_rst_tbl_size; u64 dma_mask; - const u32 *inst_iris_fmts; - u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; const struct tz_cp_config *tz_cp_config_data; u32 tz_cp_config_data_size; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c index 8f01cf7f6d49..37aee82a49f4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -36,12 +36,6 @@ static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { .fwname = "qcom/vpu/vpu20_p4.mbn", }; -static const u32 iris_fmts_vpu2_dec[] = { - V4L2_PIX_FMT_H264, - V4L2_PIX_FMT_HEVC, - V4L2_PIX_FMT_VP9, -}; - static struct platform_inst_caps platform_inst_cap_vpu2 = { .min_frame_width = 128, .max_frame_width = 8192, @@ -89,8 +83,6 @@ const struct iris_platform_data sc7280_data = { .opp_clk_tbl = sc7280_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu2_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, .tz_cp_config_data = tz_cp_config_vpu2, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), @@ -122,8 +114,6 @@ const struct iris_platform_data sm8250_data = { .opp_clk_tbl = sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu2_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), .inst_caps = &platform_inst_cap_vpu2, .tz_cp_config_data = tz_cp_config_vpu2, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index b8099d7ce556..30c95621fa0e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -50,13 +50,6 @@ static const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { .fwname = "qcom/vpu/vpu35_p4.mbn", }; -static const u32 iris_fmts_vpu3x_dec[] = { - V4L2_PIX_FMT_H264, - V4L2_PIX_FMT_HEVC, - V4L2_PIX_FMT_VP9, - V4L2_PIX_FMT_AV1, -}; - static const struct icc_info iris_icc_info_vpu3x[] = { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -109,8 +102,6 @@ const struct iris_platform_data qcs8300_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_qcs8300, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), @@ -140,8 +131,6 @@ const struct iris_platform_data sm8550_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), @@ -179,8 +168,6 @@ const struct iris_platform_data sm8650_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), @@ -210,8 +197,6 @@ const struct iris_platform_data sm8750_data = { .opp_clk_tbl = iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), @@ -247,8 +232,6 @@ const struct iris_platform_data x1p42100_data = { .opp_clk_tbl = x1p42100_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_vpu3x_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), .inst_caps = &platform_inst_cap_sm8550, .tz_cp_config_data = tz_cp_config_vpu3, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c index 99c839a0424f..e569817a0c80 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c @@ -25,12 +25,6 @@ static const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen2_s6_desc = { .fwname = "qcom/vpu/ar50lt_p1_gen2_s6.mbn", }; -static const u32 iris_fmts_ar50lt_dec[] = { - V4L2_PIX_FMT_H264, - V4L2_PIX_FMT_HEVC, - V4L2_PIX_FMT_VP9, -}; - static const struct bw_info iris_bw_table_dec_ar50lt[] = { { ((1920 * 1080) / 256) * 60, 1564000, }, { ((1920 * 1080) / 256) * 30, 791000, }, @@ -100,8 +94,6 @@ const struct iris_platform_data qcm2290_data = { .opp_clk_tbl = iris_opp_clk_table_ar50lt, /* Upper bound of DMA address range */ .dma_mask = 0xe0000000 - 1, - .inst_iris_fmts = iris_fmts_ar50lt_dec, - .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_ar50lt_dec), .inst_caps = &platform_inst_cap_ar50lt, .tz_cp_config_data = tz_cp_config_ar50lt, .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_ar50lt), diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c index 9169b1335b5c..59200ca72ded 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -83,8 +83,8 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type) switch (type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - fmt = inst->core->iris_platform_data->inst_iris_fmts; - size = inst->core->iris_platform_data->inst_iris_fmts_size; + fmt = inst->core->iris_firmware_data->dec_fmts; + size = inst->core->iris_firmware_data->dec_fmts_size; break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: if (ubwc->ubwc_enc_version) { @@ -128,8 +128,8 @@ static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type) switch (type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - fmt = inst->core->iris_platform_data->inst_iris_fmts; - size = inst->core->iris_platform_data->inst_iris_fmts_size; + fmt = inst->core->iris_firmware_data->dec_fmts; + size = inst->core->iris_firmware_data->dec_fmts_size; break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: if (ubwc->ubwc_enc_version) { -- 2.47.3