From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 102C5421F10 for ; Fri, 10 Jul 2026 11:56:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783684569; cv=none; b=lI3CIIKhiGUvLUSKe0ibv14drAnY8QJvSQ4yF3l7F7u8dDgooKK3+tT0e7eaprzEInZVixZetTNDHg/anjoRz4cyW+E8swIk4RFCQfsqNCLVwBA4HPfnqzIRub5nixLgnGh0/FlNe7nWBLaw98uY1tVPv3RDCzS5Eh496HzTx6s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783684569; c=relaxed/simple; bh=SlCJb0uWu0DEr3QM93tT1sdbU1p/RwbZ5S8JPpGqyHg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VJ+/G/O1PF4PvNbipgF19G4eUCWDHrTla0v7cToeUBfA5osjVYdtSKGj/EDdTAEBhz1kf6B7caj6RyhUdnzv/RJdXPZhbv5HOmtOmd3gEAdZ4CbP94g3mPr+xWHCxAhYCXV15b/23bsjnp9DlqQjMIE71NlSA25Z/oq3If/geXA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Cw0yDahN; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Cw0yDahN" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 300B41EDB; Fri, 10 Jul 2026 04:55:55 -0700 (PDT) Received: from e134344.cambridge.arm.com (e134344.arm.com [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 37A303F85F; Fri, 10 Jul 2026 04:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783684559; bh=SlCJb0uWu0DEr3QM93tT1sdbU1p/RwbZ5S8JPpGqyHg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cw0yDahNS7oeq2YpWsmK3uNqEQwPr3AobLCARV7JGEWc78oUNn0XdPo6PgbFopoej P8ZoEx2s859a2jYCRJysaqKDC/LUHt5BIBqK59qL010tl/3EqbqAP20zO4fouIMztc OQLiZE/XKJiLdKG6zMFq0MjevMuxmSmK1mlfFkNE= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com Subject: [PATCH v1 02/11] arm_mpam: Restore the error interrupt enable from mpam_cpu_online() Date: Fri, 10 Jul 2026 12:55:36 +0100 Message-ID: <20260710115546.29644-3-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260710115546.29644-1-ben.horgan@arm.com> References: <20260710115546.29644-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When all CPUs affine to an MSC are offline the MSC may lose register state which the driver then restores when an affine CPU comes back online. The error interrupt enable, MPAMF_ECR.INTEN, is missed. Restore MPAMF_ECR at CPU online. Fixes: 49aa621c4dca ("arm_mpam: Register and enable IRQs") Signed-off-by: Ben Horgan --- drivers/resctrl/mpam_devices.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 82966ca2a631..acfa9a4dc2fc 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1852,8 +1852,14 @@ static int mpam_cpu_online(unsigned int cpu) if (msc->reenable_error_ppi) _enable_percpu_irq(&msc->reenable_error_ppi); - if (atomic_fetch_inc(&msc->online_refs) == 0) + if (atomic_fetch_inc(&msc->online_refs) == 0) { + mutex_lock(&msc->error_irq_lock); + if (msc->error_irq_hw_enabled) + mpam_touch_msc(msc, mpam_enable_msc_ecr, msc); + mutex_unlock(&msc->error_irq_lock); + mpam_reprogram_msc(msc); + } } if (mpam_resctrl_enabled) -- 2.43.0