From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 705AC41B374 for ; Fri, 10 Jul 2026 11:56:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783684572; cv=none; b=WIKPyxjG+PkjZcK6GcQ7uT2JNFdJTQ1KdTzbTWxyehIzcV76pnM8Uwdw21hMYG3KIKozfMQCJanCKe6HcMJSHVXloSauilsmiaWl9q81BzOwo9vgZO9PSBthU6Rgck1BzmWsDKlzLauWUu3oTGCIbLVuaRNoRe3nkQQLtUCgBD0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783684572; c=relaxed/simple; bh=gywOZrzhJ41YWIQWWOF3b/dr0W/CIWVRpFcmyEH9INg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jpUorLN1mPXc9kIgoRtTLXNk2E0W6yW4Wdee9yk6ZNwfDZMt50Uf4KimMhJXAgYLWpABU9+7wpQlF1TGMS2FNsGIIsoiOBM3Ba+jrsi4FIGOHXkgFCNEi9VHmTUaryrwxvj3tISr0+R/EwsFPVCRF3bv37v5g8SN+KHOubWBkVA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=P28bDA5R; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="P28bDA5R" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DFDF32308; Fri, 10 Jul 2026 04:55:59 -0700 (PDT) Received: from e134344.cambridge.arm.com (e134344.arm.com [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EC6213F85F; Fri, 10 Jul 2026 04:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783684564; bh=gywOZrzhJ41YWIQWWOF3b/dr0W/CIWVRpFcmyEH9INg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P28bDA5R+CGGc4K7Iv7MVn248/MD3daSdui+1kYDh/4sjWaeBLf0v1AM9Ck0TwH2j eOBwzHL5JLsjnLj21U22oB7zk9MASDQD1g31XAHC5GLIt3OFUBYYFza78EjKWp+SPI i+shhLS65o2UplWaqBZ3SbwD+jcqMsLUPQBa1mI4= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com Subject: [PATCH v1 05/11] arm_mpam: Ensure MBWU counters are reset on restore Date: Fri, 10 Jul 2026 12:55:39 +0100 Message-ID: <20260710115546.29644-6-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260710115546.29644-1-ben.horgan@arm.com> References: <20260710115546.29644-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When an MSC becomes inaccessible due to cpu offline CFG_MBWU_CTL is set to zero in mpam_save_mbwu_state(). This is very likely to mean that the config will mismatch when restoring and so the monitor will be reset. However, the state may have been lost and so there are no guarantees. Ensure the reset happens by setting the reset_on_next_read and remove the unnecessary writes from mpam_save_mbwu_state(). Fixes: 41e8a14950e1 ("arm_mpam: Track bandwidth counter state for power management") Signed-off-by: Ben Horgan --- drivers/resctrl/mpam_devices.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index b34e2a368516..222fc248067e 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1648,10 +1648,13 @@ static int mpam_restore_mbwu_state(void *_ris) u64 val; struct mon_read mwbu_arg; struct mpam_msc_ris *ris = _ris; + struct msmon_mbwu_state *mbwu_state; struct mpam_msc *msc = ris->vmsc->msc; struct mpam_class *class = ris->vmsc->comp->class; for (i = 0; i < ris->props.num_mbwu_mon; i++) { + mbwu_state = &ris->mbwu_state[i]; + if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) return -EIO; @@ -1661,6 +1664,8 @@ static int mpam_restore_mbwu_state(void *_ris) mwbu_arg.type = mpam_msmon_choose_counter(class); mwbu_arg.val = &val; + mbwu_state->reset_on_next_read = true; + mpam_mon_sel_unlock(msc); __ris_msmon_read(&mwbu_arg); @@ -1696,15 +1701,11 @@ static int mpam_save_mbwu_state(void *arg) cur_flt = mpam_read_monsel_reg(msc, CFG_MBWU_FLT); cur_ctl = mpam_read_monsel_reg(msc, CFG_MBWU_CTL); - mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); - if (mpam_ris_has_mbwu_long_counter(ris)) { + if (mpam_ris_has_mbwu_long_counter(ris)) val = mpam_msc_read_mbwu_l(msc); - mpam_msc_zero_mbwu_l(msc); - } else { + else val = mpam_read_monsel_reg(msc, MBWU); - mpam_write_monsel_reg(msc, MBWU, 0); - } cfg->mon = i; cfg->pmg = FIELD_GET(MSMON_CFG_x_FLT_PMG, cur_flt); -- 2.43.0