From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABC92330B3F for ; Sat, 11 Jul 2026 02:56:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783738605; cv=none; b=XAxfv1u0j1zVV3NGglUjGNAdx65eJJ4sh5bjR1qq7wM/mSdznUQxirEgPDjgMqHtHxPMKC+FU1l6hvJht7SxlDSCrgUyn42dIJcfkSWt8SkU4AOL8m7Zp494Cs2Kmf37qNEW2l5pGKxdhmtX1Dx7U28a0ZZk1z620m9u2WWxuWk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783738605; c=relaxed/simple; bh=BG1PFICdpAljvWYeK8+LJvs9zXvpb2Spx/Q4HUyJTRs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=d+KELDim+r+ASqzXoq78zH38xrmQ/eKY8yuTpU47oslE9ev50jP5/sgX0pBECGY58Nxpd6jK2SorxPfMit9F/FeDBROxdWsOhP8knyRR39mRmDqjx9NNmhvCXxUsNDvzMATih9R8m102T33UKT0AjRUK5GYUm9NdtszggL4xWME= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QRxgR5+7; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QRxgR5+7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783738604; x=1815274604; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BG1PFICdpAljvWYeK8+LJvs9zXvpb2Spx/Q4HUyJTRs=; b=QRxgR5+7fiuOcNDcar+/fcYO6J8rh+3s7uppNbhh2/POQnwlY8p8Pf2Y JkLI+DSbQbOwHiSHyA72m/F3gUCGN25qRH1Y4FkAgHHemPj7UPeJq14B0 yJb+Vw0Pf2SkN47LAHcvbPC5AUA6YJGQ/YUltGu08v0hemQRgbK9yPJd8 yvqKmnHzvzB9Dk0UXgq0tVVOiP+265OuXLNFSfcM2u78BlsqPXEf0AVH0 13DbU45JkzUKkNmlIuVNOva77MUlJTBnJZrvs2H3pxnV+9bp9geWi6F4f TSwKgNz+ZNCJ3RwhW/ti963RJfS35Jihqu62erKxDkKrzH/8RvY40UDWz A==; X-CSE-ConnectionGUID: 2bGMcDJVRZC5Nr6LB9u1rw== X-CSE-MsgGUID: ykxP9nefR2212HM+7d2U/g== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="101986358" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="101986358" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2026 19:56:33 -0700 X-CSE-ConnectionGUID: bAaDsPe7QvSp/d7/LRM4wQ== X-CSE-MsgGUID: vVLEukHbR/eyq+BeH/4A/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="256987786" Received: from gsse-cloud1.jf.intel.com ([10.54.39.91]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2026 19:56:32 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Carlos Santa , Ryan Neph , Christian Koenig , Huang Rui , Matthew Auld , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org, =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= Subject: [PATCH v3 27/33] drm/xe: Add IOVA-based xe_res_cursor variant Date: Fri, 10 Jul 2026 19:56:13 -0700 Message-Id: <20260711025619.2540575-28-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260711025619.2540575-1-matthew.brost@intel.com> References: <20260711025619.2540575-1-matthew.brost@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce xe_res_first_iova() to walk a buffer that was DMA mapped using the IOVA-based DMA API (dma_iova_try_alloc() and friends). Such a mapping is described by a struct dma_iova_state and is a single contiguous IOVA range, so the cursor walks it as one segment. Add an is_iova flag to struct xe_res_cursor to distinguish this case. When set, xe_res_dma() returns the IOVA backing the current position (state->addr + cursor offset), xe_res_next() advances within the single contiguous segment, and xe_res_is_vram() returns false since IOVA mappings never point to same-device VRAM. The flag is explicitly cleared in the existing xe_res_first(), xe_res_first_sg() and xe_res_first_dma() initializers so stale stack values cannot leak into the new path. Cc: Carlos Santa Cc: Ryan Neph Cc: Christian Koenig Cc: Huang Rui Cc: Matthew Auld Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Simona Vetter Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Cc: Thomas Hellström Assisted-by: GitHub_Copilot:claude-opus-4.8 Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_res_cursor.h | 56 +++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_res_cursor.h b/drivers/gpu/drm/xe/xe_res_cursor.h index 0522caafd89d..f0f1d699e16e 100644 --- a/drivers/gpu/drm/xe/xe_res_cursor.h +++ b/drivers/gpu/drm/xe/xe_res_cursor.h @@ -24,6 +24,7 @@ #ifndef _XE_RES_CURSOR_H_ #define _XE_RES_CURSOR_H_ +#include #include #include @@ -67,6 +68,12 @@ struct xe_res_cursor { u64 dma_start; /** @dma_seg_size: Size of the current DMA segment. */ u64 dma_seg_size; + /** + * @is_iova: Whether the cursor walks a single contiguous IOVA + * mapping described by a struct dma_iova_state. When true, the + * DMA address is @dma_start + @start and never points to VRAM. + */ + bool is_iova; }; static struct gpu_buddy *xe_res_get_buddy(struct ttm_resource *res) @@ -93,6 +100,7 @@ static inline void xe_res_first(struct ttm_resource *res, { cur->sgl = NULL; cur->dma_addr = NULL; + cur->is_iova = false; if (!res) goto fallback; @@ -224,6 +232,7 @@ static inline void xe_res_first_sg(const struct sg_table *sg, cur->dma_addr = NULL; cur->sgl = sg->sgl; cur->mem_type = XE_PL_TT; + cur->is_iova = false; __xe_res_sg_next(cur); } @@ -255,6 +264,41 @@ static inline void xe_res_first_dma(const struct drm_pagemap_addr *dma_addr, __xe_res_dma_next(cur); cur->sgl = NULL; cur->mem_type = XE_PL_TT; + cur->is_iova = false; +} + +/** + * xe_res_first_iova() - initialize a xe_res_cursor with a dma_iova_state + * + * @state: struct dma_iova_state describing a single contiguous IOVA mapping + * @start: Start of the range + * @size: Size of the range + * @cur: cursor object to initialize + * + * Start walking over the range of an allocation that was DMA mapped using the + * IOVA-based DMA API (see dma_iova_try_alloc()). Such a mapping is a single + * contiguous IOVA range, so the cursor walks it as one segment. Subsequent + * calls to xe_res_next() advance within that range and xe_res_dma() returns + * the IOVA backing the current position. xe_res_is_vram() always returns false + * for such a cursor. + */ +static inline void xe_res_first_iova(struct dma_iova_state *state, + u64 start, u64 size, + struct xe_res_cursor *cur) +{ + XE_WARN_ON(!state); + XE_WARN_ON(start + size > dma_iova_size(state)); + + cur->node = NULL; + cur->start = start; + cur->remaining = size; + cur->size = size; + cur->dma_addr = NULL; + cur->sgl = NULL; + cur->dma_start = state->addr; + cur->dma_seg_size = dma_iova_size(state); + cur->mem_type = XE_PL_TT; + cur->is_iova = true; } /** @@ -283,6 +327,13 @@ static inline void xe_res_next(struct xe_res_cursor *cur, u64 size) return; } + if (cur->is_iova) { + /* Single contiguous IOVA segment. */ + cur->start += size; + cur->size = cur->remaining; + return; + } + if (cur->dma_addr) { cur->start += size; __xe_res_dma_next(cur); @@ -334,7 +385,7 @@ static inline void xe_res_next(struct xe_res_cursor *cur, u64 size) */ static inline u64 xe_res_dma(const struct xe_res_cursor *cur) { - if (cur->dma_addr) + if (cur->is_iova || cur->dma_addr) return cur->dma_start + cur->start; else if (cur->sgl) return sg_dma_address(cur->sgl) + cur->start; @@ -351,6 +402,9 @@ static inline u64 xe_res_dma(const struct xe_res_cursor *cur) */ static inline bool xe_res_is_vram(const struct xe_res_cursor *cur) { + if (cur->is_iova) + return false; + if (cur->dma_addr) return cur->dma_addr->proto == XE_INTERCONNECT_VRAM; -- 2.34.1