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Use qcom_mpm_offset() as the common addressing helper for both timer and pin register accesses based on that layout. vMPM has MPM_REG_* values represented as contiguous register IDs, hence replace the macros with enum qcom_mpm_reg and modify the accessor helpers accordingly. Signed-off-by: Sneh Mankad --- drivers/irqchip/irq-qcom-mpm.c | 48 ++++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 01fd1843172aa22760d359281e39f0d9394bab6d..763eddee99dc4cdd5edab22ce54808528f9ef165 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -66,11 +66,16 @@ * */ -#define MPM_REG_ENABLE 0 -#define MPM_REG_FALLING_EDGE 1 -#define MPM_REG_RISING_EDGE 2 -#define MPM_REG_POLARITY 3 -#define MPM_REG_STATUS 4 +#define MPM_TIMER_REGS 2 + +enum qcom_mpm_reg { + MPM_REG_TIMER = 0, + MPM_REG_ENABLE, + MPM_REG_FALLING_EDGE, + MPM_REG_RISING_EDGE, + MPM_REG_POLARITY, + MPM_REG_STATUS, +}; /* MPM pin map to GIC hwirq */ struct mpm_gic_map { @@ -92,18 +97,36 @@ struct qcom_mpm_priv { atomic_t cpus_in_pm; }; -static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, unsigned int reg, - unsigned int index) +static unsigned int qcom_mpm_offset(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, + unsigned int index) +{ + unsigned int reg_offset; + + /* + * Per the vMPM register map, TIMER[0..1] starts at register index 0 and all pin-specific + * registers start after the two TIMER regs. Pin-specific register IDs start at + * MPM_REG_ENABLE, so subtract it to convert to a zero-based pin-register group index. + */ + if (reg == MPM_REG_TIMER) + reg_offset = index; + else + reg_offset = MPM_TIMER_REGS + + (reg - MPM_REG_ENABLE) * priv->reg_stride + index; + + return reg_offset * sizeof(u32); +} + +static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, unsigned int index) { - unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; + unsigned int offset = qcom_mpm_offset(priv, reg, index); return readl_relaxed(priv->base + offset); } -static void qcom_mpm_write(struct qcom_mpm_priv *priv, unsigned int reg, +static void qcom_mpm_write(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, unsigned int index, u32 val) { - unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; + unsigned int offset = qcom_mpm_offset(priv, reg, index); writel_relaxed(val, priv->base + offset); @@ -144,7 +167,7 @@ static void qcom_mpm_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } -static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, unsigned int reg, +static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, enum qcom_mpm_reg reg, unsigned int index, unsigned int shift) { unsigned long flags, val; @@ -327,8 +350,7 @@ static int mpm_pd_power_cb(struct notifier_block *nb, unsigned long action, void return NOTIFY_OK; } -static int mpm_cpu_pm_callback(struct notifier_block *nfb, - unsigned long action, void *v) +static int mpm_cpu_pm_callback(struct notifier_block *nfb, unsigned long action, void *v) { struct qcom_mpm_priv *priv = container_of(nfb, struct qcom_mpm_priv, mpm_pm); int cpus_in_pm; -- 2.34.1