[PATCH] perf capstone: Fix build with Capstone versions before 6

[Leo Yan <leo.yan@arm.com>]

The commit 12c4737f55f2 ("perf capstone: Determine architecture from
e_machine") added a RISC-V mapping for Capstone disassembly.

However, the RISC-V arch and mode definitions are only available from
Capstone 6.0.0. Older Capstone headers do not define CS_ARCH_RISCV,
CS_MODE_RISCV64 or CS_MODE_RISCV32, so perf fails to build.

Guard the RISC-V mapping with a Capstone major version check. Also use
CS_MODE_RISCV_C instead of CS_MODE_RISCVC, which is the mode name used
by Capstone 6.

Fixes: 12c4737f55f2 ("perf capstone: Determine architecture from e_machine")
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
 tools/perf/util/capstone.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/perf/util/capstone.c b/tools/perf/util/capstone.c
index 9bba78ee0c5a2e6c86a97ffe69ca4db966bafd9b..99efeb40ed03621e781ef9b888321e28d237a0ca 100644
--- a/tools/perf/util/capstone.c
+++ b/tools/perf/util/capstone.c
@@ -182,10 +182,12 @@ static bool e_machine_to_capstone(uint16_t e_machine, bool is64, bool is_big_end
 		*arch = CS_ARCH_SPARC;
 		*mode |= CS_MODE_V9;
 		return true;
+#if defined(CS_VERSION_MAJOR) && CS_VERSION_MAJOR >= 6
 	case EM_RISCV:
 		*arch = CS_ARCH_RISCV;
-		*mode |= (is64 ? CS_MODE_RISCV64 : CS_MODE_RISCV32) | CS_MODE_RISCVC;
+		*mode |= (is64 ? CS_MODE_RISCV64 : CS_MODE_RISCV32) | CS_MODE_RISCV_C;
 		return true;
+#endif
 	default:
 		return false;
 	}

---
base-commit: ef3af1df4f3372bd8ad47619452a283048b3bc8d
change-id: 20260713-perf_fix_capstone_build-510dc3bfecfb

Best regards,
-- 
Leo Yan <leo.yan@arm.com>