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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-313b9ca880fsm26496089eec.23.2026.07.13.02.16.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 02:16:23 -0700 (PDT) From: Wei Deng To: Wei Deng , Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, Chen-Yu Tsai , mengshi.wu@oss.qualcomm.com, quic_chezhou@quicinc.com, cheng.jiang@oss.qualcomm.com, shuai.zhang@oss.qualcomm.com, jinwang.li@oss.qualcomm.com, xiuzhuo.shang@oss.qualcomm.com Subject: Re: [PATCH 3/3] power: sequencing: pcie-m2: Deassert W_DISABLE2# when no UART serdev is created Date: Mon, 13 Jul 2026 14:46:16 +0530 Message-Id: <20260713091616.4092086-1-wei.deng@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=TbymcxQh c=1 sm=1 tr=0 ts=6a54ace9 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=cm27Pg_UAAAA:8 a=EUspDBNiAAAA:8 a=M_wy9YA4QbPrr36y3cgA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEzMDA5NiBTYWx0ZWRfX4bx2qBOmjEwU FKAh1PtoZ1uQv+G4eIh7VXTUMuyA7YWB7VlRzzw0dLBeqcFoSV+GU8wIjHOYsCFf9fS9tWML7/f OjnthPKB+u1fhiacBpVyh/AjulDdP98= X-Proofpoint-GUID: y9Wj9Zbn4zEuiwbr3knrWu1Tuk9zQGJ_ X-Proofpoint-ORIG-GUID: y9Wj9Zbn4zEuiwbr3knrWu1Tuk9zQGJ_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEzMDA5NiBTYWx0ZWRfXw581ixoGPB4I n58OetIhkxtmDJFzajSEhz51wSwQVMHtV+l1SETJX3kzr0WjS8jWXb9itnvS6HhSbbPug9++1Dl QvL3b8kjQNt9gexlgEaEPCvUA1JdAaeoktfTdcO7VLwX7J+YLdAEQ2i/TVYtDLPiI2YAJHp1cZo 81VVOnTdhuFFQOJmdQYOdBpqcUri+5le7xmQs7fIQRvBAblxu/yAra96iRIQ/KMQ+Ump4WmURrV HrzdTaIW9YY3HS7/IUq13J280cIBNyhVtxim+30aydwNUZnuFcxyiLjPzQB18nBGCsTqZPgABkk HkBaFTwabWsLd9u6KJY1eU8DQPP/zZlnjDHiCwn8lb0QkN3ZRp2D8gfK4ZQStYaF/iSbxMpx/+B kSmvDMQ4pUKs1+yqlKLS7q0llbX8/rzstEdRLVEeLQJKyQGl2vZJTq/mU5GwoWMMkBzfZ7L4kJJ PRPkrshscCXIrf+hY9Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-13_02,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607130096 On Thu, 9 Jul 2026, Dmitry Baryshkov wrote: > On Thu, Jul 09, 2026 at 12:59:42PM +0530, Wei Deng wrote: > > The pwrseq_m2_pci_ids[] table lists PCIe BT devices that use UART as the > > BT transport and need a UART serdev created by the driver. When a PCIe > > device under the M.2 connector does not match any entry in this table, > > no UART serdev is created. > > > > However, the BT subsystem of such a device may still require W_DISABLE2# > > to be deasserted to power up. Rather than adding every possible non-UART > > BT device ID to the table, add an else branch that deasserts W_DISABLE2# > > whenever a PCIe device is detected under the connector but does not match > > a UART BT entry. This allows any BT interface on the card (USB or other) > > to enumerate without requiring explicit knowledge of its device ID. > > > > The primary use case is USB BT variants of combo chips that share the > > same PCIe device ID as their UART counterpart (e.g. WCN7851 NCM865 USB, > > sub 0x3378, vs NCM865A UART, sub 0x337c): no UART serdev is needed, but > > W_DISABLE2# must be deasserted so the USB BT device can enumerate. > > Instead of forcibly toggling it, would it be more sensible to tie pwrseq > into the USB too? The onboard-usb-dev implements the same idea (of > powering up the USB device), but it predates pwrseq. > > > Reassert W_DISABLE2# symmetrically when the PCIe device is removed. > > > > Validated on Hamoa EVK (IQ-X7181-EVK) with WCN7851 NCM865 USB card > > (sub 0x3378): without this change GPIO116 (W_DISABLE2#) stays low and > > no BT interface appears; with this change GPIO116 is driven high and the > > USB BT device enumerates and comes up via btusb. > > > > Signed-off-by: Wei Deng > > --- > > drivers/power/sequencing/pwrseq-pcie-m2.c | 33 +++++++++++++++++++++---------- > > 1 file changed, 23 insertions(+), 10 deletions(-) > > > > -- > With best wishes > Dmitry > Hi Dmitry, There is a patch series from Chen-Yu Tsai that appears to implement what you suggested: [PATCH v4 00/14] arm64: mediatek: Add M.2 E-key slot on Chromebooks https://lore.kernel.org/all/20260709095726.704448-1-wenst@chromium.org/ We have been testing this on the Qualcomm Hamoa IoT EVK with both UART BT and USB BT M.2 cards. Is this the direction you had in mind? Thanks, Wei Deng -- Best Regards, Wei Deng