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Mon, 13 Jul 2026 04:15:45 -0700 From: Ashish Mhetre To: , , , , , , , CC: , , , , , Ashish Mhetre Subject: [PATCH v6 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Date: Mon, 13 Jul 2026 11:15:39 +0000 Message-ID: <20260713111543.1462161-1-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC7:EE_|DS0PR12MB7945:EE_ X-MS-Office365-Filtering-Correlation-Id: eb7a7450-308a-4d80-2740-08dee0d01de9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|7416014|82310400026|23010399003|18002099003|6133799003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: uPtJ36HziNEDSteegfoPFiHYy+MSDbfuSQ+p7p+jWlBxGotYLYHMjJHGjl9dbMzbJhCFeUmvs9x7Yo0jU/sE/clD0jzrblbmORFX2SSeWkLypnu1DlmzaY1+hYiJOsn9x1MLh4mDwkXhRW2cW3byRqgX15bN+cQdPUDugIOStNTfoyhxayaa5JIe+GGMFN+IQXM7grfyYDKzXhoTt7uCMp7cVYbUa7S9SKqiUrSPbgSpqgcO0NqbHsdT0Gndu9VucqHhgnp7CrkZbgFrL2OkAlxyb+FQBF8Z58ulNjvNq9D+31fPVT3elNmCTpksZswbGqeV92dZA2+wI3BLz/o+6xEcY+xtzfonKaerlRZYTEq12/efjsjIFCl2gYKyZ6k4+SkT9co9Jk8RtO6jBzbURDa9Rk6wxstGBNZFUdmIz/ViqROZy1o3sxTCDbJaKu6UTrauE/I2yhjQ5yRU+25qfda8IKpHqC79MWzTqWWErxUZY8sSKbnHNzeZEj/eGmR/TSep8cvPE8muUrtLVm9mMLaWCl/dyhj/3fQXzaP4pcFOe7ApHzEpB6cQ5qLkdb+3JkmYU7SumOR8fAeK9g/ZVbWShPb1OEc6ob83wgvabbNJyLyob2DercQXHBBWPb385oBOgL/50ONLqITmNfO7ldnBZJi1V+aljkx3m55galOsdbCiTiVPIaVa79JjE31vB11vU7lejXN8R9LmUljqLA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(7416014)(82310400026)(23010399003)(18002099003)(6133799003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DI7mXy9ow7+DVANVcwNi5qSyIUatQmHcTZbVj5w379DLJ/WlafTK6ti+9WF5BSYzbI8ouL3RfhgvxtxFJtkkfPze8HqldzPtdiYL3z7n8gigOv0mVqkMUdgiQ+7fKiqOic/2CLbpYf0JREfiqn6T70pM8QPw0d1ymIvrrqj1qgTaiAajmoTlgZ1tuV6zCSMeWZprvrz/HOf+lbT9sjS29Bv/Z9imjH7eQdd1xPgW6XnQ6kEFlPqIhTH+/rD4jKqjYWeEnufbDD+U8Amsys95Ge1wUCcA1+bkJCsLPpl3gTP+Dkntarc590JtR84OXckpBGJwQZt6AzNYoF+M69PpJfatboDkjZLgwmZw7J9fWpWb3C2JqVk1anWLwV0pVIR2HilIEu8i8xy/66NtMyoZHLEsVVmW8S/vtbad4UfdQNfjL6ez0fAexey1Kee5yhPK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2026 11:15:59.1283 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb7a7450-308a-4d80-2740-08dee0d01de9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7945 Nvidia Tegra264 SMMUs are affected by an erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue must execute only after the first issue's CMD_SYNC has completed, giving the sequence: TLBI/CFGI ... CMD_SYNC TLBI/CFGI ... CMD_SYNC ATC_INV is not affected and must not be doubled. The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot be detected from hardware ID. Tegra264 is device-tree-only (no ACPI/IORT support), so detection is purely by compatible string. This series is structured as a small refactor + infrastructure + enable sequence so that each step is reviewable in isolation: 1/3 Pure refactor (no functional change): lift the existing force-sync conditions out of arm_smmu_cmdq_batch_add_cmd_p() into a new arm_smmu_cmdq_batch_force_sync() helper, so that adding another condition (in patch 2) is a one-line addition. Authored by Nicolin Chen. 2/3 Add the workaround infrastructure without enabling it. Defines the file-local arm_smmu_erratum_repeat_tlbi_cfgi_key static key with an inline erratum description, the shared arm_smmu_erratum_cmd_needs_repeating() predicate, the arm_smmu_cmdq_issue_cmdlist() wrapper that can re-issue matching cmdlists, the batch-helper force-sync condition, and the iommufd batching split for mixed command classes. 3/3 Enable the workaround for the existing "nvidia,tegra264-smmu" compatible and document the erratum in silicon-errata.rst. The series applies cleanly on linux-next/master (base-commit below). Changes since v5: - Move arm_smmu_erratum_cmd_needs_repeating() into arm-smmu-v3.c and leave a declaration-only stub in arm-smmu-v3.h. Make arm_smmu_erratum_repeat_tlbi_cfgi_key file-local static and drop jump_label.h from the header. - Add an inline erratum/workaround description at the static key, referenced from arm_smmu_cmdq_batch_force_sync(). - Drop the misleading !n comment above arm_smmu_cmdq_issue_cmdlist(); keep the defensive !n guard. - Remove the unused smmu parameter from the predicate. - Tweak 2/3 commit-message wording ("commit" vs "patch"). - Add Reviewed-by: Nicolin Chen on 3/3. Changes since v4: - Drop ARM_SMMU_OPT_REPEAT_TLBI_CFGI entirely: the option bit was set and read on the exact same "nvidia,tegra264-smmu" compatible as the static key, so it added no per-instance signal that the static key did not already carry. The predicate now gates purely on arm_smmu_erratum_repeat_tlbi_cfgi_key. - Reorder the series so the compatible-string detection lands last, once all the infrastructure exists: 1/3 factor out force_sync helper (unchanged) 2/3 add static key + WAR functions (no functional change) 3/3 enable the key on nvidia,tegra264-smmu + silicon-errata Split the old v4 "Detect" and "Issue twice" patches accordingly. - Update the /* See ARM_SMMU_OPT_REPEAT_TLBI_CFGI */ comment inside arm_smmu_cmdq_batch_force_sync() to reference the static key description instead. Changes since v3: - Drop the cmds->num == 0 early-return so the refactor is truly "no functional change". - Rename ARM_SMMU_OPT_TLBI_TWICE -> ARM_SMMU_OPT_REPEAT_TLBI_CFGI and rephrase its kdoc to be hardware-agnostic. - Rename arm_smmu_cmd_needs_tlbi_twice() -> arm_smmu_erratum_cmd_needs_repeating() and drop the kdoc above it. - Replace the explicit opcode switch with a single range check opcode >= CMDQ_OP_CFGI_STE && opcode < CMDQ_OP_ATC_INV. - Introduce arm_smmu_erratum_repeat_tlbi_cfgi_key static key: the predicate gates on it first so unaffected kernels pay only a single static_branch_unlikely() check. - Drop the verbose Tegra264-specific comments above arm_vsmmu_can_batch_cmd() and inside the batch helper. - Document the erratum in Documentation/arch/arm64/silicon-errata.rst. - Guard the repeat path in arm_smmu_cmdq_issue_cmdlist() with an n > 0 check so cmds[0] is never inspected on an empty cmdlist. - Drop the carried Reviewed-by tags now that the patch shape has changed; re-review appreciated. Changes since v2: - Split into a 3-patch series (refactor / detect / apply) to keep each step small and bisectable. - Move the classifier to arm-smmu-v3.h as static inline so the iommufd file can share it. - Add arm_vsmmu_can_batch_cmd() to split iommufd batches at "needs repeating" transitions so the per-batch decision based on the first command stays correct under mixed user input. - Spell out in the commit message why detection is via DT and not via IIDR/ACPI. Changes since v1: - Detect the erratum from the existing "nvidia,tegra264-smmu" compatible instead of adding a new property. - Centralise the doubling at the CMDQ submission layer and only apply it to CFGI/TLBI (not ATC_INV). - Drop the binding/dtsi patches accordingly. Ashish Mhetre (2): iommu/arm-smmu-v3: Introduce CFGI/TLBI-repeat workaround infrastructure iommu/arm-smmu-v3: Enable CFGI/TLBI-repeat workaround on Tegra264 Nicolin Chen (1): iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Documentation/arch/arm64/silicon-errata.rst | 2 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 15 +++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 75 ++++++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 4 files changed, 81 insertions(+), 12 deletions(-) base-commit: bee763d5f341b99cf472afeb508d4988f62a6ca1 -- 2.50.1